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1. 发明授权

US11916063B2 Electrostatic discharge protection device 有权
公开(公告)号：US11916063B2
公开(公告)日：2024-02-27
申请号：US17397583
申请日：2021-08-09
申请人： SK hynix Inc.
发明人： Joung Cheul Choi , Chang Seok Song
IPC分类号： H01L27/02 , H02H9/04 , H01L29/74
CPC分类号： H01L27/0277 , H01L27/0255 , H01L27/0262 , H01L27/0274 , H01L27/0288 , H01L27/0292 , H01L29/7408 , H02H9/046 , H01L29/7404
摘要： An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

2. 发明授权

US11916061B2 Electronic circuit 有权
公开(公告)号：US11916061B2
公开(公告)日：2024-02-27
申请号：US18095728
申请日：2023-01-11
申请人： STMicroelectronics SA
发明人： Louise De Conti , Philippe Galy
IPC分类号： H01L27/02 , H01L27/12 , H01L29/74
CPC分类号： H01L27/0262 , H01L27/0277 , H01L27/1203 , H01L29/7436
摘要： An electronic circuit includes a first electronic component formed above a buried insulating layer of a substrate and a second electronic component formed under the buried insulating layer. The insulating layer is thoroughly crossed by a semiconductor well. The semiconductor well electrically couples a terminal of the first electronic component to a terminal of the second electronic component.

3. 发明申请

US20180166438A1 INTEGRATED CIRCUITS WITH HIGH CURRENT CAPACITY AND METHODS FOR PRODUCING THE SAME 审中-公开
公开(公告)号：US20180166438A1
公开(公告)日：2018-06-14
申请号：US15376754
申请日：2016-12-13
申请人： Globalfoundries Singapore Pte. Ltd.
发明人： Handoko Linewih , Chao Cheng
IPC分类号： H01L27/02 , H01L29/10
CPC分类号： H01L27/0277 , H01L29/1083 , H01L29/78
摘要： Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a source and a drain defined within a body isolation well. A gate overlies the body isolation well between the source and the drain, and an isolating structure is formed within the body isolation well. The isolating structure sections the source into a plurality of source sections with the plurality of source sections adjacent to one gate.

4. 发明授权

US09876006B2 Semiconductor device for electrostatic discharge protection 有权
公开(公告)号：US09876006B2
公开(公告)日：2018-01-23
申请号：US15188962
申请日：2016-06-21
申请人： UNITED MICROELECTRONICS CORP.
发明人： Kun-Yu Tai , Li-Cih Wang , Tien-Hao Tang
IPC分类号： H01L27/02 , H01L29/06
CPC分类号： H01L27/0277 , H01L29/0623 , H01L29/0653
摘要： A semiconductor device for electrostatic discharge (ESD) protection includes a doped well, a drain region, a source region, a first doped region and a guard ring. The doped well is disposed in a substrate and has a first conductive type. The drain region is disposed in the doped well and has a second conductive type. The source region is disposed in the doped well and has the second conductive type, wherein the source region is separated from the drain region. The doped region is disposed in the doped well between the drain region and the source region, wherein the doped region has the first conductive type and is in contact with the doped well and the source region. The guard ring is disposed in the doped well and has the first conductive type.

5. 发明申请

US20170117267A1 ELECTROSTATIC DISCHARGE PROTECTION DEVICE 审中-公开
公开(公告)号：US20170117267A1
公开(公告)日：2017-04-27
申请号：US15284576
申请日：2016-10-04
申请人： NXP B.V.
发明人： Gijs Jan DE RAAD , Suzana DOMINGUES , Harrie Martinus Maria HORSTINK
IPC分类号： H01L27/02 , H01L29/78 , H01L29/10 , H02H9/04
CPC分类号： H01L27/0266 , H01L27/0277 , H01L29/0692 , H01L29/1095 , H01L29/7831 , H01L29/7835 , H02H9/046
摘要： An electrostatic discharge protection device and a method of making the same. The device includes a device area located on a semiconductor substrate. The device also includes an array of coextensive, laterally spaced fingers located within the device area. Each finger includes an elongate source and an elongate drain separated by an elongate gate. The fingers are electrically connected in parallel for conducting an electrostatic discharge current during an electrostatic discharge event. The device further includes a plurality of body contact regions. A layout of the body contact regions is graded such that a greater number of the body contact regions, larger body contact regions, or both are located towards a periphery of the device area than towards a central part of the device area. The layout of the body contact regions may encourage triggering of the electrostatic discharge protection device within the central part of the device area.

6. 发明申请

US20170084603A1 ELECTROSTATIC DISCHARGE PROTECTION SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20170084603A1
公开(公告)日：2017-03-23
申请号：US14924708
申请日：2015-10-27
申请人： UNITED MICROELECTRONICS CORP.
发明人： Chung-Yu Huang , Kuan-Cheng Su , Tien-Hao Tang , Ping-Jui Chen , Po-Ya Lai
IPC分类号： H01L27/02 , H01L27/088
CPC分类号： H01L27/0277 , H01L27/0259 , H01L27/0886 , H01L29/0619 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/42372 , H01L29/7816 , H01L29/7835 , H01L29/7851
摘要： An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, at least a first doped region formed in the source region, and at least a second doped region formed in the drain region. The source region, the drain region and the second doped region include a first conductivity type, and the first doped region includes a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other. The second doped region is electrically connected to the first doped region.

7. 发明授权

US09478531B2 Semiconductor device comprising an ESD protection device, an ESD protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device 有权
标题翻译：包括ESD保护器件，ESD保护电路，集成电路和制造半导体器件的方法的半导体器件
公开(公告)号：US09478531B2
公开(公告)日：2016-10-25
申请号：US14419029
申请日：2012-08-03
申请人： Jean Philippe Laine , Patrice Besse
发明人： Jean Philippe Laine , Patrice Besse
IPC分类号： H01L29/66 , H01L27/02
CPC分类号： H01L27/0259 , H01L27/0277 , H01L29/6625
摘要： A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.
摘要翻译：半导体器件包括ESD保护器件。在N阱中，两个P +掺杂区形成ESD保护器件的寄生晶体管的集电极和发射极。 P +掺杂区域之间的N阱区域形成寄生晶体管的基极。在距离P +掺杂区域一定距离处，提供了N +掺杂区域。 N +掺杂区域和晶体管的基极之间的N阱形成ESD保护器件的寄生电阻。晶体管的N +掺杂区域和发射极通过电连接彼此耦合。 ESD保护器件具有有限的快速恢复特性，并具有很好的触发电压。

8. 发明申请

US20160133621A1 SEMICONDUCTOR DEVICE AND AN ELECTRONIC APPARATUS 有权
标题翻译：半导体器件和电子设备
公开(公告)号：US20160133621A1
公开(公告)日：2016-05-12
申请号：US14934949
申请日：2015-11-06
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
发明人： Yi Liu , Jun Wang , Ying Ma , Bin Lu , Huijuan Cheng
IPC分类号： H01L27/02
CPC分类号： H01L27/0262 , H01L27/0277 , H01L29/0649 , H01L29/6609 , H01L29/7391 , H01L29/7436 , H01L29/87
摘要： A semiconductor device includes a P-type substrate, and an N-well in the P-type substrate. A first N+ diffusion region is located in the P-type substrate, and a first P+ diffusion region is located in the N-well. A second P+ diffusion region is located across a boundary between the P-type substrate and the N-well. A first gate electrode overlies the N-well between the first P+ diffusion regions and the second P+ diffusion region. A second gate electrode overlies the P-type substrate between the second P+ diffusion region and the first N+ diffusion region. The first P+ diffusion region, the N-well, the P-type substrate, and the first N+ diffusion region form an SCR (Silicon-Controlled rectifier) device. The first P+ diffusion region, the second P+ diffusion region, and the first gate electrode form a PMOS transistor. The second P+ diffusion region, the first N+ diffusion region, and the second gate electrode form a gated diode.
摘要翻译：半导体器件包括P型衬底和P型衬底中的N阱。第一N +扩散区位于P型衬底中，第一P +扩散区位于N阱中。第二P +扩散区位于P型衬底和N阱之间的边界上。第一栅电极覆盖在第一P +扩散区和第二P +扩散区之间的N阱。第二栅电极覆盖在第二P +扩散区和第一N +扩散区之间的P型衬底。第一P +扩散区，N阱，P型衬底和第一N +扩散区形成SCR（硅控整流器）装置。第一P +扩散区，第二P +扩散区和第一栅电极形成PMOS晶体管。第二P +扩散区，第一N +扩散区和第二栅电极形成门控二极管。

9. 发明授权

US09306389B2 ESD protection circuit 有权
标题翻译： ESD保护电路
公开(公告)号：US09306389B2
公开(公告)日：2016-04-05
申请号：US14677508
申请日：2015-04-02
申请人： MediaTek Inc.
发明人： Chien-Hui Chuang
IPC分类号： H02H9/00 , H02H9/04 , H01L27/02 , H03K19/003
CPC分类号： H02H9/04 , H01L27/0266 , H01L27/0277 , H03K19/00315
摘要： An electrostatic discharge protection circuit is provided. First NMOS transistor is coupled to a power line. Second NMOS transistor is coupled between the first NMOS transistor and a ground. Detection unit provides a detection signal when an ESD event occurs at the power line. Trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal. Discharge path is formed from the power line to the ground via the first and second NMOS transistors. First PMOS transistor is coupled between the power line and a gate of the second NMOS transistor. Third NMOS transistor is coupled between the ground and the gate of the second NMOS transistor. Second PMOS transistor is coupled between the gates of the first and second NMOS transistors. Third PMOS transistor is coupled between the power line and the first PMOS transistor.
摘要翻译：提供静电放电保护电路。第一NMOS晶体管耦合到电源线。第二NMOS晶体管耦合在第一NMOS晶体管和地之间。当电源线发生ESD事件时，检测单元提供检测信号。触发单元响应于检测信号依次接通第二NMOS晶体管和第一NMOS晶体管。放电路径由电源线经由第一和第二NMOS晶体管形成到地。第一PMOS晶体管耦合在电源线和第二NMOS晶体管的栅极之间。第三NMOS晶体管耦合在第二NMOS晶体管的接地和栅极之间。第二PMOS晶体管耦合在第一和第二NMOS晶体管的栅极之间。第三PMOS晶体管耦合在电源线和第一PMOS晶体管之间。

10. 发明授权

US09293451B2 Integrated circuit electrical protection device 有权
标题翻译：集成电路电气保护装置
公开(公告)号：US09293451B2
公开(公告)日：2016-03-22
申请号：US13682558
申请日：2012-11-20
申请人： Michael A. Stockinger
发明人： Michael A. Stockinger
IPC分类号： H02H3/20 , H01L27/02 , H01L27/06
CPC分类号： H01L27/0277 , H01L27/0629
摘要： An integrated circuit electrical protection device includes a semiconductor substrate, and first, second, and third doped regions of a first polarity in the semiconductor substrate. The first and second doped regions are separated from one another by a first body region having a second polarity and the second and third doped regions are separated from one another by a second body region having the second polarity. The first and second polarities are different from one another. A fourth doped region of the second polarity directly abutting and in contact with the third doped region. A first gate structure is formed over the first body region between the first and second doped regions. A second gate structure is formed over the second body region between the second and third doped regions.
摘要翻译：集成电路电气保护装置包括半导体衬底和半导体衬底中具有第一极性的第一，第二和第三掺杂区域。第一和第二掺杂区域通过具有第二极性的第一体区彼此分离，并且第二和第三掺杂区域通过具有第二极性的第二体区彼此分离。第一和第二极性彼此不同。第二极性的第四掺杂区直接邻接并与第三掺杂区接触。在第一和第二掺杂区域之间的第一体区上形成第一栅极结构。第二栅极结构形成在第二和第三掺杂区域之间的第二体区上。

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