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1. 发明申请

US20180337268A1 CHANNEL STOP IMP FOR FINFET DEVICE 审中-公开
公开(公告)号：US20180337268A1
公开(公告)日：2018-11-22
申请号：US15925390
申请日：2018-03-19
申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION , SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
发明人： FEI ZHOU
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06
CPC分类号： H01L29/66803 , H01L21/30625 , H01L29/0638 , H01L29/1083 , H01L29/66545 , H01L29/66871 , H01L29/785
摘要： A method of manufacturing a semiconductor device includes providing a semiconductor structure including a substrate, a semiconductor fin on the substrate, and a dummy gate structure on the semiconductor fin. The dummy gate structure includes a dummy gate dielectric layer on the semiconductor fin and a dummy gate on the dummy gate dielectric layer. The method also includes forming an interlayer dielectric layer on the semiconductor substrate, planarizing the interlayer dielectric layer to expose an upper surface of the dummy gate, and performing a first doping implant into the semiconductor fin through the dummy gate to form an anti-puncture region in the semiconductor fin. The anti-puncture region has an upper surface lower than an upper surface of a trench isolation portion surrounding the semiconductor fin to prevent a punch through of a source and drain, reducing a current leakage and parasitic capacitance of the semiconductor device.

2. 发明授权

US10038063B2 Tunable breakdown voltage RF FET devices 有权
公开(公告)号：US10038063B2
公开(公告)日：2018-07-31
申请号：US14300884
申请日：2014-06-10
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Vibhor Jain , Qizhi Liu , John J. Pekarik
IPC分类号： H01L29/417 , H01L29/78 , H01L29/66 , H01L21/28 , H01L29/812 , H01L27/12 , H01L29/51 , H01L29/49 , H01L29/47
CPC分类号： H01L29/41775 , H01L21/28052 , H01L27/1203 , H01L29/47 , H01L29/4933 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/66848 , H01L29/66871 , H01L29/7835 , H01L29/812 , H01L2924/0002 , H01L2924/00
摘要： A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

3. 发明授权

US09728620B2 Semiconductor device having metal gate structure and fabrication method thereof 有权
公开(公告)号：US09728620B2
公开(公告)日：2017-08-08
申请号：US14831247
申请日：2015-08-20
申请人： Semiconductor Manufacturing International (Shanghai) Corporation
发明人： Ming Zhou
IPC分类号： H01L29/66 , H01L29/49 , H01L29/51 , H01L29/423 , H01L21/28 , H01L21/321 , H01L23/532 , H01L21/768
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/321 , H01L21/76846 , H01L21/76856 , H01L23/53223 , H01L29/42372 , H01L29/517 , H01L29/66545 , H01L29/66553 , H01L29/66871 , H01L29/7833
摘要： The present disclosure provides a semiconductor device including a metal gate structure and formation method thereof. The semiconductor device includes a substrate and a dielectric layer disposed on the substrate. The dielectric layer includes a trench. A diffusion barrier layer is disposed over a bottom surface and sidewall surfaces of the trench in the dielectric layer. The diffusion barrier layer includes at least a titanium-nitride stacked layer. The titanium-nitride stacked layer includes a TiNx layer disposed over the bottom surface and the sidewall surfaces of the trench, a TiN layer on the TiNx layer, and a TiNy layer on the TiN layer, x 1. A metal gate is filled in the trench and disposed on the diffusion barrier layer.

4. 发明申请

US20160013290A1 TURNABLE BREAKDOWN VOLTAGE RF FET DEVICES 审中-公开
公开(公告)号：US20160013290A1
公开(公告)日：2016-01-14
申请号：US14864020
申请日：2015-09-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Vibhor JAIN , Qizhi LIU , John J. PEKARIK
IPC分类号： H01L29/66 , H01L23/66
CPC分类号： H01L29/41775 , H01L21/28052 , H01L27/1203 , H01L29/47 , H01L29/4933 , H01L29/518 , H01L29/665 , H01L29/66659 , H01L29/66848 , H01L29/66871 , H01L29/7835 , H01L29/812 , H01L2924/0002 , H01L2924/00
摘要： A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.

5. 发明申请

US20150325690A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体器件结构及其形成方法
公开(公告)号：US20150325690A1
公开(公告)日：2015-11-12
申请号：US14273994
申请日：2014-05-09
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yung-Tsun LIU
IPC分类号： H01L29/78 , H01L21/3105 , H01L29/66
CPC分类号： H01L29/66545 , H01L21/26506 , H01L21/28518 , H01L21/3105 , H01L21/31053 , H01L21/76814 , H01L21/76831 , H01L29/165 , H01L29/517 , H01L29/665 , H01L29/66553 , H01L29/66636 , H01L29/66871 , H01L29/78 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure further includes a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer, a metal gate over the gate dielectric layer, a first insulating layer over the metal gate and a second insulating layer over the first insulating layer. Materials of the first insulating layer and the second insulating layer are different. The semiconductor device structure also includes spacers over opposite sidewalls of the gate stack. The spacers and the metal gate surround a recess, and the first insulating layer and the second insulating layer are in the recess.
摘要翻译：提供半导体器件结构。半导体器件结构包括半导体衬底。半导体器件结构还包括在半导体衬底上的栅极堆叠。栅极堆叠包括栅极电介质层，栅极介电层上的金属栅极，金属栅极之上的第一绝缘层和位于第一绝缘层上的第二绝缘层。第一绝缘层和第二绝缘层的材料不同。该半导体器件结构还包括在栅叠层的相对侧壁上的间隔物。间隔物和金属栅极围绕凹部，并且第一绝缘层和第二绝缘层位于凹部中。

6. 发明授权

US08105889B2 Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions 有权
标题翻译：制造晶体管的方法包括自对准栅电极和源/漏区
公开(公告)号：US08105889B2
公开(公告)日：2012-01-31
申请号：US12509855
申请日：2009-07-27
申请人： R. Peter Smith , Scott T. Sheppard
发明人： R. Peter Smith , Scott T. Sheppard
IPC分类号： H01L21/338
CPC分类号： H01L29/2003 , B82Y10/00 , H01L21/26553 , H01L21/28587 , H01L29/15 , H01L29/402 , H01L29/42316 , H01L29/42376 , H01L29/66462 , H01L29/66871 , H01L29/66878 , H01L29/7787 , H01L29/812
摘要： Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
摘要翻译：形成III族氮化物晶体管器件的方法包括在III族氮化物半导体层上形成保护层，在保护层上形成通孔以暴露出III族氮化物半导体层的一部分，并形成掩模栅极保护层。掩模门包括具有比通孔宽度大的宽度的上部，并且具有延伸到通孔中的下部。所述方法还包括使用掩模栅极作为植入掩模将源极/漏极区域注入到III族氮化物半导体层中。

7. 发明申请

US20120012893A1 SEMICONDUCTOR TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体晶体管及其制造方法
公开(公告)号：US20120012893A1
公开(公告)日：2012-01-19
申请号：US13177913
申请日：2011-07-07
申请人： Kazushi NAKAZAWA
发明人： Kazushi NAKAZAWA
IPC分类号： H01L29/812 , H01L21/338 , B82Y99/00
CPC分类号： H01L29/8128 , H01L29/42316 , H01L29/66462 , H01L29/66871 , H01L29/7787
摘要： To provide a semiconductor transistor without variation in threshold voltage of an FET and a method of manufacturing the semiconductor transistor, the semiconductor transistor includes: a substrate; a first compound semiconductor layer formed above the substrate; a second compound semiconductor layer formed on the first compound semiconductor layer and having a bandgap larger than a bandgap of the first compound semiconductor layer; an oxygen-doped region formed by doping at least part of the second compound semiconductor layer with oxygen; a third compound semiconductor layer formed on the second compound semiconductor layer; a source electrode electrically connected to the first compound semiconductor layer; a drain electrode electrically connected to the first compound semiconductor layer; and a gate electrode formed on and in contact with the oxygen-doped region.
摘要翻译：为了提供没有FET的阈值电压的变化的半导体晶体管和制造半导体晶体管的方法，所述半导体晶体管包括：衬底; 形成在所述基板上方的第一化合物半导体层; 形成在所述第一化合物半导体层上并具有大于所述第一化合物半导体层的带隙的带隙的第二化合物半导体层; 通过用氧将至少部分第二化合物半导体层掺杂而形成的氧掺杂区; 形成在第二化合物半导体层上的第三化合物半导体层; 电极，与所述第一化合物半导体层电连接; 电连接到所述第一化合物半导体层的漏电极; 以及形成在氧掺杂区上并与氧掺杂区接触的栅电极。

8. 发明申请

US20110097886A1 SEMICONDUCTOR DEVICE WITH MUSHROOM ELECTRODE AND MANUFACTURE METHOD THEREOF 有权
标题翻译：具有MUSHROOM电极的半导体器件及其制造方法
公开(公告)号：US20110097886A1
公开(公告)日：2011-04-28
申请号：US12985742
申请日：2011-01-06
申请人： Kozo Makiyama , Naoya IKECHI , Takahiro Tan
发明人： Kozo Makiyama , Naoya IKECHI , Takahiro Tan
IPC分类号： H01L21/3205
CPC分类号： H01L21/0274 , H01L21/28114 , H01L21/28264 , H01L21/28587 , H01L29/42316 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66871 , H01L29/78 , Y10S430/143 , Y10S438/949 , Y10S438/95 , Y10S438/951
摘要： A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.
摘要翻译：半导体器件具有：半导体衬底，具有电流流过的一对电流输入/输出区域; 形成在所述半导体基板上并具有栅电极开口的绝缘膜; 以及通过所述栅电极开口形成在所述半导体基板上的蘑菇栅极电极结构，所述蘑菇栅电极结构具有杆和形成在所述杆上的头部，所述杆在所述半导体衬底上沿着电流方向具有有限的尺寸，并且具有向前锥形形状向上并沿着电流方向单调地增加尺寸，头部具有沿着电流方向逐步扩大的尺寸，并且杆在栅极电极开口中接触半导体衬底并且在至少一个位置附近骑绝缘膜杆的相对端之一沿着当前方向。

9. 发明申请

US20050116302A1 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US20050116302A1
公开(公告)日：2005-06-02
申请号：US10985057
申请日：2004-11-10
申请人： Yoshitaka Kamo , Tetsuo Kunii
发明人： Yoshitaka Kamo , Tetsuo Kunii
IPC分类号： H01L21/28 , H01L21/338 , H01L29/417 , H01L29/812 , H01L29/745
CPC分类号： H01L29/66871 , H01L29/41725 , H01L29/812
摘要： A field effect transistor includes a semiconductor substrate having an active region, a source region, and a drain region at an upper portion of the substrate. The active region is located between the source and drain regions. A gate electrode is located on the active region. A source electrode is located on the source region and forms an ohmic contact with the source region. A drain electrode has a base part on and in ohmic contact with the drain region and an extended part having edge closer to the gate electrode than to a boundary between the active region and the drain region. An insulating film is located between the boundary and the extended part and has a thickness that increases along a direction from the drain electrode toward the gate electrode in a step-by-step or continuous manner.
摘要翻译：场效应晶体管包括在衬底的上部具有有源区，源极区和漏极区的半导体衬底。有源区位于源区和漏区之间。栅电极位于有源区上。源电极位于源极区上并与源极区形成欧姆接触。漏极电极具有与漏极区域基极和欧姆接触的基极部分，以及具有比有源区域和漏极区域之间的边界更靠近栅电极的延伸部分的延伸部分。绝缘膜位于边界和延伸部分之间，并且具有沿着从漏电极朝向栅电极的方向逐步或连续地增加的厚度。

10. 发明申请

US20040152289A1 Semiconductor device with mushroom electrode and manufacture method thereof 有权
公开(公告)号：US20040152289A1
公开(公告)日：2004-08-05
申请号：US10768092
申请日：2004-02-02
申请人： FUJITSU LIMITED , FUJITSU QUANTUM DEVICES LIMITED
发明人： Kozo Makiyama , Takahiro Tan
IPC分类号： H01L021/3205
CPC分类号： H01L21/0274 , H01L21/28114 , H01L21/28264 , H01L21/28587 , H01L29/42316 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66871 , H01L29/78 , Y10S430/143 , Y10S438/949 , Y10S438/95 , Y10S438/951
摘要： A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

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