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1. 发明授权

US12028021B2 Current mode signal path of an integrated radio frequency pulse generator 有权
公开(公告)号：US12028021B2
公开(公告)日：2024-07-02
申请号：US17354718
申请日：2021-06-22
申请人： International Business Machines Corporation
发明人： Sudipto Chakraborty , David James Frank , John Francis Bulzacchelli , Rajiv Joshi , Daniel Joseph Friedman
IPC分类号： H03D7/14 , H03D3/00 , H03M1/66 , H04B1/00
CPC分类号： H03D7/1458 , H03D3/008 , H03D7/1441 , H03M1/66 , H04B1/0007 , H03D2200/0033 , H03D2200/0047 , H03D2200/009
摘要： A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

2. 发明授权

US09893924B2 Module for a radio receiver 有权
公开(公告)号：US09893924B2
公开(公告)日：2018-02-13
申请号：US15062141
申请日：2016-03-06
申请人： NXP B.V.
发明人： Zahir Smail , Olivier Jamin , Carol Herve
IPC分类号： H04B1/10 , H04L27/26 , H04B1/00 , H03D3/00 , H04L27/38
CPC分类号： H04L27/265 , H03D3/008 , H03D3/009 , H03D2200/005 , H03D2200/006 , H04B1/0017 , H04L1/206 , H04L27/3863 , H04L27/3872 , H04L27/3881
摘要： The disclosure relates to a module for a radio receiver. The module comprises an input terminal; an output terminal; a main signal path for communicating in-phase and quadrature signals between the input terminal and the output terminal; and a second signal path. The second signal path is connected in parallel with the main signal path and is configured to: extract in-phase and quadrature signals from the main signal path; filter the extracted in-phase and quadrature signals; detect an error in the filtered, extracted in-phase and quadrature signals; and apply a correction to in-phase and quadrature signals on the main signal path based on the error.

3. 发明申请

US20160182160A1 Harmonic Reject Receiver Architecture and Mixer 审中-公开
公开(公告)号：US20160182160A1
公开(公告)日：2016-06-23
申请号：US15056229
申请日：2016-02-29
申请人： MaxLinear, Inc.
发明人： Kishore Seendripu , Raymond Montemayor , Sheng Ye , Glenn Chang , Curtis Ling
IPC分类号： H04B15/00 , H04J1/18 , H04L27/34
CPC分类号： H04B1/26 , H03D3/007 , H03D3/008 , H03D3/009 , H03D7/14 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/165 , H03D7/166 , H03D2200/0086 , H03H11/22 , H04B1/10 , H04B1/109 , H04B1/12 , H04B1/30 , H04B15/00 , H04J1/18 , H04L27/34
摘要： Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

4. 发明申请

US20160099737A1 Harmonic Reject Receiver Architecture and Mixer 审中-公开
公开(公告)号：US20160099737A1
公开(公告)日：2016-04-07
申请号：US14966660
申请日：2015-12-11
申请人： MaxLinear, Inc.
发明人： Kishore Seendripu , Raymond Montemayor , Sheng Ye , Glenn Chang , Curtis Ling
IPC分类号： H04B1/30 , H03D7/14 , H03D7/16
CPC分类号： H04B1/26 , H03D3/007 , H03D3/008 , H03D3/009 , H03D7/14 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/165 , H03D7/166 , H03D2200/0086 , H03H11/22 , H04B1/10 , H04B1/109 , H04B1/12 , H04B1/30 , H04B15/00 , H04J1/18 , H04L27/34
摘要： Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

5. 发明申请

US20150365128A1 SYSTEM AND METHOD FOR LEAKAGE SUPPRESSION BY SEPARATING IMPAIRMENTS FROM THE RECEIVE PATH 审中-公开
标题翻译：通过从接收路径分离影响来进行泄漏抑制的系统和方法
公开(公告)号：US20150365128A1
公开(公告)日：2015-12-17
申请号：US14737191
申请日：2015-06-11
申请人： Texas Instruments Incorporated
发明人： Hunsoo CHOO , Nikolaus KLEMMER , Jaiminkumar MEHTA
IPC分类号： H04B1/525 , H04B1/44
CPC分类号： H04B1/525 , H03D3/008 , H04B1/30
摘要： A system for reducing a local oscillator leakage component. The system includes a transmitter channel to transmit data modulated using a transmitter local oscillator frequency. A transmitted signal includes a transmitter local oscillator leakage component. The system also includes a receiver channel to receive the transmitted signal using a receiver local oscillator signal having a frequency offset from the transmitter local oscillator frequency. The received signal includes the transmitter local oscillator leakage component isolated from one or more receiver impairments. The system further includes a feedback loop from the receiver channel to the transmitter channel to identify a power of the isolated transmitter local oscillator leakage component and to generate a local oscillator leakage cancellation signal based on the identified power.
摘要翻译：用于减少本地振荡器泄漏分量的系统。该系统包括用于发送使用发射机本地振荡器频率调制的数据的发射机信道。发射信号包括发射机本地振荡器泄漏分量。该系统还包括接收机信道，用于使用具有来自发射机本地振荡器频率的频率偏移的接收机本地振荡器信号来接收发射信号。所接收的信号包括与一个或多个接收器损伤隔离的发射器本地振荡器泄漏部件。该系统还包括从接收器通道到发射器通道的反馈回路，以识别隔离发射器本地振荡器泄漏分量的功率，并且基于所识别的功率产生本地振荡器泄漏消除信号。

6. 发明授权

US08586461B2 Systems and methods providing spur avoidance in a direct conversion tuner architecture 有权
标题翻译：在直接转换调谐器架构中提供无回波的系统和方法
公开(公告)号：US08586461B2
公开(公告)日：2013-11-19
申请号：US12632571
申请日：2009-12-07
申请人： Jan-Michael Stevenson
发明人： Jan-Michael Stevenson
IPC分类号： H04N5/14 , H04N5/50
CPC分类号： H04B15/04 , H03D1/2245 , H03D3/008 , H03D3/009 , H04B1/0082 , H04B1/30 , H04B1/401 , H04B2215/065 , H04L25/061 , H04L27/364 , H04N5/455 , H04N5/46 , H04N21/42638 , H04N21/4382 , H04N21/6112
摘要： Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.
摘要翻译：示出了提供实现直接频率转换的多模调谐器架构的系统和方法。实施例提供高度集成的配置，其中在单个集成电路中提供低噪声放大器，调谐器，模拟和数字信道滤波器以及模拟解调器功能。实施例的LNA实现具有无缝切换的多路径配置，以在满足噪声和线性设计参数的同时提供期望的增益控制。本发明的实施例实现了同相和正交（IQ）均衡和多模信道化滤波器架构，以便于直接频率转换的使用。实施例实现了使用其中系统时钟，采样时钟频率，本地振荡器（LO）参考时钟频率等等是可动态移动的时钟信号生成架构来改进调谐器系统操作和输出的杂散避免技术。

7. 发明授权

US08374568B2 Harmonic reject receiver architecture and mixer 有权
标题翻译：谐波抑制接收机架构和混频器
公开(公告)号：US08374568B2
公开(公告)日：2013-02-12
申请号：US13568286
申请日：2012-08-07
申请人： Kishore Seendripu , Raymond Montemayor , Sheng Ye , Glenn Chang , Curtis Ling
发明人： Kishore Seendripu , Raymond Montemayor , Sheng Ye , Glenn Chang , Curtis Ling
IPC分类号： H04B1/10 , H04B15/06
CPC分类号： H04B1/26 , H03D3/007 , H03D3/008 , H03D3/009 , H03D7/14 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/165 , H03D7/166 , H03D2200/0086 , H03H11/22 , H04B1/10 , H04B1/109 , H04B1/12 , H04B1/30 , H04B15/00 , H04J1/18 , H04L27/34
摘要： Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.
摘要翻译：本文公开了采用谐波抑制混频器处理谐波丰富输入信号的接收机架构和方法。所公开的接收机，混频器和方法使得接收机能够实现切换混频器的优点，同时大大降低了混频器对不需要的谐波的响应。谐波混频器可以包括耦合到输入信号的多个混频器。可以从单个本地振荡器输出产生本地振荡器信号的多个相位。每个相都可用于驱动混合器之一的输入。混频器输出可以组合以产生具有谐波抑制的频率转换输出。

8. 发明申请

US20120300887A1 HARMONIC REJECT RECEIVER ARCHITECTURE AND MIXER 有权
标题翻译： HARMONIC REJECT RECEIVER建筑和混合器
公开(公告)号：US20120300887A1
公开(公告)日：2012-11-29
申请号：US13568562
申请日：2012-08-07
申请人： Kishore Seendripu , Raymond Montemayor , Sheng Ye , Glenn Chang , Curtis Ling
发明人： Kishore Seendripu , Raymond Montemayor , Sheng Ye , Glenn Chang , Curtis Ling
IPC分类号： H04B1/16
CPC分类号： H04B1/26 , H03D3/007 , H03D3/008 , H03D3/009 , H03D7/14 , H03D7/1441 , H03D7/1458 , H03D7/1475 , H03D7/165 , H03D7/166 , H03D2200/0086 , H03H11/22 , H04B1/10 , H04B1/109 , H04B1/12 , H04B1/30 , H04B15/00 , H04J1/18 , H04L27/34
摘要： Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.
摘要翻译：本文公开了采用谐波抑制混频器处理谐波丰富输入信号的接收机架构和方法。所公开的接收机，混频器和方法使得接收机能够实现切换混频器的优点，同时大大降低了混频器对不需要的谐波的响应。谐波混频器可以包括耦合到输入信号的多个混频器。可以从单个本地振荡器输出产生本地振荡器信号的多个相位。每个相都可用于驱动混合器之一的输入。混频器输出可以组合以产生具有谐波抑制的频率转换输出。

9. 发明授权

US08260227B2 Direct conversion receiver and DC offset concellation method 失效
标题翻译：直接转换接收机和直流偏移组合方法
公开(公告)号：US08260227B2
公开(公告)日：2012-09-04
申请号：US12136169
申请日：2008-06-10
申请人： Chinq-Shiun Chiu
发明人： Chinq-Shiun Chiu
IPC分类号： H04B1/00 , H04B15/00 , H04B1/10
CPC分类号： H04B1/30 , H03D3/008
摘要： A direct conversion receiver and a DC offset cancellation method are provided. An RF module receives a transmission signal to generate an RF signal. A mixer converts the RF signal to a mixer output comprising baseband and imaginary parts. A filter module filters out the imaginary part of the mixer output and adjusts gain of the baseband part to generate a baseband signal. A calibrator performs a calibration to determine a mismatch value of the mixer. A static DC offset canceller provides a constant offset compensation according to the mismatch value; wherein the mismatch value is used to minimize component mismatching effects of the mixer.
摘要翻译：提供直接转换接收器和DC偏移消除方法。 RF模块接收发送信号以产生RF信号。混频器将RF信号转换成包括基带和虚部的混频器输出。滤波器模块滤除混频器输出的虚部，并调整基带部分的增益以产生基带信号。校准器执行校准以确定混合器的失配值。静态DC偏移消除器根据不匹配值提供恒定的偏移补偿; 其中使用失配值来最小化混合器的组件失配效应。

10. 发明授权

US08203653B2 Integrated analog video receiver 失效
标题翻译：集成模拟视频接收器
公开(公告)号：US08203653B2
公开(公告)日：2012-06-19
申请号：US12191905
申请日：2008-08-14
申请人： Weijie Yun , Samuel Sheng , Dennis G. Yee
发明人： Weijie Yun , Samuel Sheng , Dennis G. Yee
IPC分类号： H04N5/44
CPC分类号： H03D3/008 , H03D7/165 , H03D2200/0047 , H04L25/061 , H04L27/063 , H04N5/44 , H04N5/455 , H04N5/50 , H04N5/63
摘要： An analog video receiver implemented in an integrated circuit device. The analog video receiver includes an amplifier to amplify an analog video signal having a desired carrier frequency, and a mixing circuit to mix the amplified analog video signal with a complex sinusoid having a frequency substantially equal to the carrier frequency.
摘要翻译：在集成电路器件中实现的模拟视频接收器。模拟视频接收机包括用于放大具有期望载波频率的模拟视频信号的放大器，以及混合电路，用于将放大的模拟视频信号与具有基本上等于载波频率的频率的复数正弦曲线混合。

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