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1. 发明申请

US20180262374A1 FINITE IMPULSE RESPONSE ANALOG RECEIVE FILTER WITH AMPLIFIER-BASED DELAY CHAIN 审中-公开
公开(公告)号：US20180262374A1
公开(公告)日：2018-09-13
申请号：US15453774
申请日：2017-03-08
申请人： CREDO TECHNOLOGY GROUP LIMITED
发明人： Lawrence Chi Fung Cheng , Haihui Luo
IPC分类号： H04L27/01 , H03F3/19 , H03F3/45 , H03G3/30
CPC分类号： H04L27/01 , H03F3/193 , H03F3/211 , H03F3/45201 , H03F2200/451 , H03F2203/45361 , H03G5/28 , H03H11/26 , H03H15/02 , H04L25/03031 , H04L25/03044 , H04L25/03878
摘要： High-data rate channel interface modules and equalization methods employing a finite impulse response (FIR) analog receive filter. Embodiments include an illustrative channel interface module having multiple amplifier-based delay units arranged in a sequential chain to convert an analog input signal into a set of increasingly-delayed analog signals that are weighted and combined together with the analog input signal to form an equalized signal; and a symbol decision element operating on the equalized signal to obtain a sequence of symbol decisions. An interface that extracts received data from the sequence of symbol decisions. The delay units may employ one or more delay cells each having a common-source amplifier stage followed by a source follower output stage, the two stages providing approximately equal portions of the propagation delay. An enhanced gate-to-drain capacitance in the common-source amplifier may increase propagation delay while reducing bandwidth limitations.

2. 发明授权

US09954698B1 Efficient resource sharing in a data stream processing device 有权
公开(公告)号：US09954698B1
公开(公告)日：2018-04-24
申请号：US15374541
申请日：2016-12-09
申请人： Hughes Network Systems, LLC
发明人： Tony Chu Huang , Ninad Kelkar
IPC分类号： H03H11/26 , H03H17/00 , G06F5/06 , H04L25/03
CPC分类号： H04L25/03025 , G06F5/06 , H03H11/26 , H03H17/0009 , H03H17/0294 , H03H17/04 , H03H17/06 , H03H2017/0488 , H04L2025/03484
摘要： A data stream processing device including a first tapped delay line which outputs data values received via a first data input on N first taps, wherein N is two or more; a second tapped data delay line which outputs data values received via a second data input on N second taps; a first processing unit including N first delayed data inputs and which generates a first data output based on the N first delayed data inputs; a second processing unit including N second delayed data inputs and which generates a second data output based on the N second delayed data inputs; and control circuitry including a mode selection input, and which is coupled to in response to the mode selection input receiving a signal indicating a first mode, simultaneously couple each of the first taps to a respective one of the first delayed data inputs and couple each of the second taps to a respective one of the second delayed data inputs, and in response to the mode select input not receiving a signal indicating the first mode, simultaneously couple one of the first taps to one of the second delayed data inputs and couple one of the second taps to one of the first data inputs.

3. 发明授权

US08929429B2 Adaptive pade filter and transceiver 有权
标题翻译：自适应滤波器和收发器
公开(公告)号：US08929429B2
公开(公告)日：2015-01-06
申请号：US12905912
申请日：2010-10-15
申请人： Hiroshi Takatori , Albert Vareljian , Oleksiy Zabroda
发明人： Hiroshi Takatori , Albert Vareljian , Oleksiy Zabroda
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159 , H04L25/03 , H03H11/26 , H03H11/46 , H03H15/02
CPC分类号： H04L25/03038 , H03H11/26 , H03H11/46 , H03H15/02 , H03H21/0001 , H04B3/32 , H04L1/0047 , H04L25/03057 , H04L25/03133 , H04L25/03343 , H04L2025/03477 , H04L2025/0349 , H04L2025/03503 , H04L2025/03598
摘要： According to an embodiment of the disclosure, a communication transmitter and receiver include an adaptive filter and a decision feedback equalizer as well as cross-talk cancellers. The adaptive filter is configured to receive an input signal and includes a continuous analog delay circuit with a plurality of Padé-based delay elements.
摘要翻译：根据本公开的实施例，通信发射机和接收机包括自适应滤波器和判决反馈均衡器以及串扰消除器。自适应滤波器被配置为接收输入信号并且包括具有多个基于Padé的延迟元件的连续模拟延迟电路。

4. 发明申请

US20140049306A1 SIGNAL TRANSMISSION CIRCUITS 有权
标题翻译：信号传输电路
公开(公告)号：US20140049306A1
公开(公告)日：2014-02-20
申请号：US13719016
申请日：2012-12-18
申请人： SK HYNIX INC.
发明人： Kwan Su SHON
IPC分类号： H03H11/26
CPC分类号： H03H11/26 , H03K19/00361
摘要： A signal transmission circuit includes a pre-driver and a driver. The pre-driver is configured to generate a first drive signal in response to a first delay signal and a first selection signal and to generate a second drive signal in response to a second delay signal, a second selection signal, and a pulse signal. The driver is configured to drive a transmission signal in response to the first and second drive signals. The first delay signal is enabled at a second time which is later than a first time when an input signal is received, the second delay signal is enabled at a third time which is later than the second time, and the pulse signal is enabled at a fourth time which is delayed by a predetermined delay period from the first time.
摘要翻译：信号传输电路包括预驱动器和驱动器。预驱动器被配置为响应于第一延迟信号和第一选择信号而产生第一驱动信号，并响应于第二延迟信号，第二选择信号和脉冲信号产生第二驱动信号。驱动器被配置为响应于第一和第二驱动信号来驱动发送信号。第一延迟信号在比接收到输入信号的第一时间晚的第二时间使能，第二延迟信号在晚于第二时间的第三时间被使能，并且脉冲信号在一个第四次从第一次延迟预定的延迟时间。

5. 发明授权

US08508285B2 Analog delay lines and adaptive biasing 有权
公开(公告)号：US08508285B2
公开(公告)日：2013-08-13
申请号：US13612454
申请日：2012-09-12
申请人： Feng Lin
发明人： Feng Lin
IPC分类号： H02J1/00
CPC分类号： H03K5/133 , H03H11/26 , H03H11/265 , H03K5/131
摘要： Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.

6. 发明授权

US08289062B2 Analog delay lines and adaptive biasing 有权
标题翻译：模拟延迟线和自适应偏置
公开(公告)号：US08289062B2
公开(公告)日：2012-10-16
申请号：US12883893
申请日：2010-09-16
申请人： Feng Lin
发明人： Feng Lin
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03H11/26 , H03H11/265 , H03K5/131
摘要： Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.
摘要翻译：描述了模拟延迟线和模拟延迟系统（例如并入模拟延迟线的DLL）的示例，以及用于自适应偏置的电路和方法。描述自适应偏置的实施例，并且可以在启动期间产生用于模拟延迟线的偏置信号。偏置信号可以部分地基于模拟延迟线的操作频率。

7. 发明申请

US20120119808A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING METHOD THEROF 有权
标题翻译：半导体集成电路及其工作方法
公开(公告)号：US20120119808A1
公开(公告)日：2012-05-17
申请号：US13279408
申请日：2011-10-24
申请人： Atsushi MOTOZAWA , Takayuki TSUKAMOTO , Tatsuji MATSUURA , Yuichi OKUDA
发明人： Atsushi MOTOZAWA , Takayuki TSUKAMOTO , Tatsuji MATSUURA , Yuichi OKUDA
IPC分类号： H03H11/26
CPC分类号： H04B1/40 , H03H11/26 , H03K5/133
摘要： An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer.
摘要翻译：集成电路配备有接收混频器和信号发生器。多级延迟电路响应于接收载波信号而产生多个时钟脉冲。相位检测单元检测特定时钟脉冲的电压电平和在特定时钟脉冲之前产生的预定数量的时钟脉冲的电压电平之间的差异，从而检测特定时钟脉冲的预定相位。时钟生成单元的选择器从时钟脉冲信号输出分别具有多个相位的多个选择时钟脉冲信号。第一信号合成逻辑电路对选择时钟脉冲执行逻辑运算，从而产生提供给接收混频器的本地信号。

8. 发明申请

US20120068753A1 ANALOG DELAY LINES AND ADAPTIVE BIASING 有权
标题翻译：模拟延时线和自适应偏移
公开(公告)号：US20120068753A1
公开(公告)日：2012-03-22
申请号：US12883893
申请日：2010-09-16
申请人： Feng Lin
发明人： Feng Lin
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , H03H11/26 , H03H11/265 , H03K5/131
摘要： Examples of analog delay lines and analog delay systems, such as DLLs incorporating analog delay lines are described, as are circuits and methods for adaptive biasing. Embodiments of adaptive biasing are described and may generate a bias signal for an analog delay line during start-up. The bias signal may be based in part on the frequency of operation of the analog delay line.
摘要翻译：描述了模拟延迟线和模拟延迟系统（例如并入模拟延迟线的DLL）的示例，以及用于自适应偏置的电路和方法。描述自适应偏置的实施例，并且可以在启动期间产生用于模拟延迟线的偏置信号。偏置信号可以部分地基于模拟延迟线的操作频率。

9. 发明授权

US08054876B2 Active delay line 有权
标题翻译：主动延时线
公开(公告)号：US08054876B2
公开(公告)日：2011-11-08
申请号：US11329265
申请日：2006-01-10
申请人： Huan-Shang Tsai
发明人： Huan-Shang Tsai
IPC分类号： H03H7/30
CPC分类号： H03H11/26 , H03H11/28
摘要： A delay line for deployment in an equalizer to insert a delay in a signal received by the delay line employs a plurality of cascaded delay stages where the delay per stage provided by an active unit-gain amplifier in each stage that provides sufficient impedance mismatch between the delay stages without substantial deterioration of the frequency response of the client signal undergoing deterioration of the frequency response of the client signal undergoing delay.
摘要翻译：用于部署在均衡器中以延迟由延迟线接收的信号的延迟的延迟线采用多个级联延迟级，其中由每个级中的有源单位增益放大器提供的每级提供的延迟，其在所述延迟线之间提供足够的阻抗失配延迟阶段，而客户端信号经受延迟的客户端信号的频率响应恶化的频率响应的实质性恶化。

10. 发明授权

US07990197B2 Internal clock driver circuit 有权
标题翻译：内部时钟驱动电路
公开(公告)号：US07990197B2
公开(公告)日：2011-08-02
申请号：US12573624
申请日：2009-10-05
申请人： Kang Youl Lee
发明人： Kang Youl Lee
IPC分类号： H03H11/26
CPC分类号： H03H11/26
摘要： An internal clock signal driver circuit includes a delay block that delays a rising clock signal and a falling clock signal, and outputs a delayed rising clock signal and a delayed falling clock signal, a rising DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed rising clock signal, and outputs a rising DLL clock signal, and a falling DLL clock signal generating block that receives and combines the rising clock signal, the falling clock signal, and the delayed falling clock signal, and outputs a falling DLL clock signal.
摘要翻译：一个内部时钟信号驱动电路包括延迟上升时钟信号和一个下降时钟信号的延迟块，并输出一个延迟的上升时钟信号和一个延迟的下降时钟信号，一个上升的DLL时钟信号产生块，接收并组合上升时钟信号，下降时钟信号和延迟的上升时钟信号，并输出上升的DLL时钟信号，以及下降的DLL时钟信号产生块，接收并组合上升时钟信号，下降时钟信号和延迟的下降时钟信号，并输出下降的DLL时钟信号。

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