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1. 发明申请

US20180278270A1 CODING AND DECODING METHOD AND DEVICE, AND SYSTEM 审中-公开
公开(公告)号：US20180278270A1
公开(公告)日：2018-09-27
申请号：US15990180
申请日：2018-05-25
申请人： Huawei Technologies Co., Ltd.
发明人： Xiaoshu SI , Dao PAN , Fanglin SUN , Xiaofeng ZHANG , Tao OUYANG
IPC分类号： H03M13/17 , H04L1/00 , H03M13/00 , H03M13/11 , H03M13/35 , H03M13/23 , H03M13/15 , H03M13/29
CPC分类号： H03M13/17 , H03M13/1102 , H03M13/1515 , H03M13/23 , H03M13/2957 , H03M13/35 , H03M13/353 , H03M13/611 , H03M13/618 , H03M13/6516 , H04L1/0041 , H04L1/0046 , H04L1/0075
摘要： Embodiments of the present disclosure provide an FEC coding and decoding method and device, and a system. A transmit end determines a forward error correction FEC coding type according to a length of to-be-coded data in burst data, and performs coding according to the determined FEC coding type. A receive end determines a forward error correction FEC decoding type according to a length of to-be-decoded data in burst data, and performs decoding according to the determined FEC decoding type. The FEC coding and decoding method provided in the embodiments of the present disclosure improves utilization of a communication resource is improved, and saves a communication resource.

2. 发明授权

US10014880B2 Coding and decoding method and device, and system 有权
公开(公告)号：US10014880B2
公开(公告)日：2018-07-03
申请号：US14864338
申请日：2015-09-24
申请人： Huawei Technologies Co., Ltd.
发明人： Xiaoshu Si , Dao Pan , Fanglin Sun , Xiaofeng Zhang , Tao Ouyang
IPC分类号： H03M13/17 , H03M13/11 , H03M13/35 , H03M13/00 , H04L1/00 , H03M13/15 , H03M13/23 , H03M13/29
CPC分类号： H03M13/17 , H03M13/1102 , H03M13/1515 , H03M13/23 , H03M13/2957 , H03M13/35 , H03M13/353 , H03M13/611 , H03M13/618 , H03M13/6516 , H04L1/0041 , H04L1/0046 , H04L1/0075
摘要： Embodiments of the present disclosure provide an FEC coding and decoding method and device, and a system. A transmit end determines a forward error correction FEC coding type according to a length of to-be-coded data in burst data, and performs coding according to the determined FEC coding type. A receive end determines a forward error correction FEC decoding type according to a length of to-be-decoded data in burst data, and performs decoding according to the determined FEC decoding type. The FEC coding and decoding method provided in the embodiments of the present disclosure improves utilization of a communication resource is improved, and saves a communication resource.

3. 发明申请

US20170288700A1 BCH DECORDER IN WHICH FOLDED MULTIPLIER IS EQUIPPED 有权
公开(公告)号：US20170288700A1
公开(公告)日：2017-10-05
申请号：US15221083
申请日：2016-07-27
申请人： Korea University Research and Business Foundation
发明人： Jongsun Park , Hoyoung Tang
IPC分类号： H03M13/15
CPC分类号： H03M13/152 , H03M13/1105 , H03M13/1525 , H03M13/1545 , H03M13/158 , H03M13/17 , H03M13/2927 , H03M13/37
摘要： Provided is a BCH decoder in which a folded multiplier is equipped. The BCH decoder may include a key equation solver including a plurality of multipliers. The multiplier includes a plurality of calculation blocks configured to perform a calculation operation. Each of the calculation blocks repeatedly performs a calculation operation of a calculation stage for a plurality of calculation stages, outputs one output value on the basis of at least one input value in each calculation stage, and is connected to at least one another calculation block to transfer an output value of a current calculation stage as an input value of the at least one another calculation block in a next calculation stage.

4. 发明授权

US09710324B2 Dual in-line memory modules (DIMMs) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC 有权
公开(公告)号：US09710324B2
公开(公告)日：2017-07-18
申请号：US14857491
申请日：2015-09-17
申请人： QUALCOMM Incorporated
发明人： Michael Raymond Trombley
IPC分类号： G06F11/10 , H03M13/17
CPC分类号： G06F11/1012 , H03M13/17
摘要： A dual in-line memory module (DIMM) supporting storage of a data indicator(s) in an error correcting code (ECC) storage unit dedicated to storing an ECC. The DIMM is configured to provide a burst ECC storage unit striped in a burst data storage unit. The DIMM is configured to stripe a received burst data word across a burst data word storage unit at a write data address for a write operation. The DIMM is also configured to stripe a received burst ECC word for the burst data word across the burst ECC storage unit at the write data address in fewer bits than a number of data bit cells in the burst ECC storage unit. In this manner, the DIMM can store at least one data indicator for a burst data word in an extra, leftover bit(s) in the burst ECC storage unit.

5. 发明申请

US20170149449A1 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND 16-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 审中-公开
公开(公告)号：US20170149449A1
公开(公告)日：2017-05-25
申请号：US15426940
申请日：2017-02-07
申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
发明人： Sung-Ik PARK , Sun-Hyoung KWON , Bo-Mi LIM , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC分类号： H03M13/11 , H03M13/27 , H03M13/00 , H03M13/17
CPC分类号： H03M13/1165 , H03M13/1105 , H03M13/17 , H03M13/2792 , H03M13/6522 , H04L1/0041 , H04L1/0071
摘要： A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.

6. 发明申请

US20170149448A1 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND 256-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME 审中-公开
公开(公告)号：US20170149448A1
公开(公告)日：2017-05-25
申请号：US15426927
申请日：2017-02-07
申请人： Electronics and Telecommunications Research Institute
发明人： Sung-Ik PARK , Sun-Hyoung KWON , Jae-Young LEE , Heung-Mook KIM , Nam-Ho HUR
IPC分类号： H03M13/11 , H03M13/27 , H03M13/00 , H03M13/17
CPC分类号： H03M13/1165 , H03M13/17 , H03M13/255 , H03M13/27 , H03M13/2778 , H03M13/2792 , H03M13/618 , H03M13/6522
摘要： A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

7. 发明授权

US09654143B2 Consecutive bit error detection and correction 有权
公开(公告)号：US09654143B2
公开(公告)日：2017-05-16
申请号：US14308107
申请日：2014-06-18
申请人： Intel Corporation
发明人： Guillem Sole , Roger Espasa , Sorin Iacobovici , Brian Hickmann , Wei Wu , Thomas Fletcher
IPC分类号： G06F11/10 , H03M13/09 , H03M13/17 , H03M13/19 , H03M13/29
CPC分类号： H03M13/09 , G06F11/1012 , H03M13/17 , H03M13/19 , H03M13/29
摘要： Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.

8. 发明授权

US09602136B2 Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same 有权
公开(公告)号：US09602136B2
公开(公告)日：2017-03-21
申请号：US14636053
申请日：2015-03-02
申请人： Electronics and Telecommunications Research Institute
发明人： Sung-Ik Park , Sun-Hyoung Kwon , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
IPC分类号： H03M13/11 , H03M13/25 , H03M13/27 , H03M13/00 , H03M13/53
CPC分类号： H03M13/1165 , H03M13/17 , H03M13/255 , H03M13/27 , H03M13/2778 , H03M13/2792 , H03M13/618 , H03M13/6522
摘要： A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.

9. 发明申请

US20150370636A1 CONSECUTIVE BIT ERROR DETECTION AND CORRECTION 有权
标题翻译：协调位错误检测和修正
公开(公告)号：US20150370636A1
公开(公告)日：2015-12-24
申请号：US14308107
申请日：2014-06-18
申请人： Guillem Sole , Roger Espasa , Sorin Iacobovici , Brian Hickmann , Wei Wu , Thomas Fletcher
发明人： Guillem Sole , Roger Espasa , Sorin Iacobovici , Brian Hickmann , Wei Wu , Thomas Fletcher
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H03M13/09 , G06F11/1012 , H03M13/17 , H03M13/19 , H03M13/29
摘要： Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values. The parity checker is to detect a parity error in a data value stored in the first storage structure using a parity value corresponding to the data value. The ECC checker is to generate a syndrome. The error corrector is to detect and correct consecutive bit errors in the data value using the syndrome.
摘要翻译：公开了用于连续位错检测和校正的发明的实施例。在一个实施例中，一种装置包括存储结构，第二存储结构，奇偶校验器，纠错码（ECC）检查器和纠错器。第一存储结构是存储多个数据值，多个奇偶校验值和多个ECC值，每个奇偶校验值对应于多个数据值之一，每个奇偶校验值的第一位对应于第一对应数据值的多个部分中的相应数据值的多个部分中的第一部分与相应数据值的多个部分中的第二部分进行交织，其中每个奇偶校验值的第二位对应于相应数据值的多个部分中的第二个，每个ECC值对应于多个数据值之一。奇偶校验器使用与数据值相对应的奇偶校验值来检测存储在第一存储结构中的数据值中的奇偶校验错误。 ECC检查器是产生综合征。错误校正器是使用综合征来检测和纠正数据值中的连续位错误。

10. 发明申请

US20150095746A1 TRANSMITTING APPARATUS, RECEIVING APPARATUS, TRANSMITTING METHOD, AND RECEIVING METHOD 审中-公开
标题翻译：发送装置，接收装置，发送方法和接收方法
公开(公告)号：US20150095746A1
公开(公告)日：2015-04-02
申请号：US14515002
申请日：2014-10-15
申请人： PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
发明人： Yutaka MURAKAMI , Shutai Okamura
IPC分类号： H04L1/00 , H03M13/17 , H03M13/37 , H03M13/11
CPC分类号： H04L1/0041 , H03M13/1154 , H03M13/17 , H03M13/2703 , H03M13/2707 , H03M13/353 , H03M13/356 , H03M13/373 , H03M13/3761 , H03M13/6306 , H03M13/6356 , H04L1/0045 , H04L1/0057 , H04L1/08 , H04L1/1819 , H04L1/1877
摘要： A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q−1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q−1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from a information packets, where n satisfies the formula Kmax×(q−1)≦n.
摘要翻译：具有改进的使用LDPC-CC的损失校正能力的损失校正编码装置包括重排单元，其根据约束长度Kmax和校验多项式的编码率（q-1）/ q重新排列包含在n个信息分组中的信息数据在损失校正编码单元中使用的损失校正码。具体地说，重新布置单元以不同的信息包中包含重排后的连续的Kmax×（q-1）个信息数据的方式重新排列信息数据。重排单元将信息数据从信息包中分配出来，其中n满足公式Kmax×（q-1）＆nlE; n。

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