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1. 发明申请

US20190200376A1 CYCLICAL OBSTRUCTION COMMUNICATION SYSTEM 审中-公开
公开(公告)号：US20190200376A1
公开(公告)日：2019-06-27
申请号：US16024435
申请日：2018-06-29
申请人： ViaSat, Inc.
发明人： Donald Wilcoxson , John O'Neill , Daniel Chester , Brian Sleight , Changping Li
IPC分类号： H04W72/12 , H04W76/10 , H04L1/00 , H04L1/08 , H04B7/185
CPC分类号： H04W72/1257 , H04B7/18506 , H04B7/18586 , H04L1/0002 , H04L1/0009 , H04L1/0034 , H04L1/0051 , H04L1/08 , H04W76/10
摘要： Techniques for improving data rates at mobile terminals that are subject to periodic channel interruptions in a beyond-line-of-sight communication system are disclosed, including improved encoding and decoding systems that identify blockages and modify receiver operation during blockages to reduce data errors. In certain embodiments, encoding, symbol mapping, interleaving, and use of unique periodic identifiers function to enable a series of packets that may be received in a blockage impaired channel with reduced errors.

2. 发明申请

US20180343082A1 EARLY TERMINATION OF LOW-DENSITY PARITY-CHECK (LDPC) DECODING 审中-公开
公开(公告)号：US20180343082A1
公开(公告)日：2018-11-29
申请号：US15607260
申请日：2017-05-26
申请人： SK Hynix Inc.
发明人： Chenrong Xiong , Fan Zhang , Yu Cai , Aman Bhatia , Naveen Kumar , Abhiram Prabahkar
IPC分类号： H04L1/00 , H03M13/00 , H03M13/11
CPC分类号： H03M13/1108 , H03M13/05 , H03M13/1111 , H03M13/1128 , H03M13/1575 , H03M13/255 , H03M13/2948 , H03M13/2951 , H03M13/3746 , H03M13/3753 , H03M13/458 , H03M13/616 , H04L1/005 , H04L1/0051 , H04L1/0057
摘要： Techniques for improving the latency or processing performance of an error correction system are described. In an example, the error correction system implements LDPC decoding and uses an early termination rule to determine whether the LDPC decoding should be terminated prior to reaching a maximum number of iterations. The early termination rule involves various parameters that relate to the syndrome of the decoded LDPC codeword at each iteration. These parameters include the number of the current decoding iteration and the weight of the syndrome at the current iteration. For example, the early termination rule specifies that the LDPC decoding should be terminated prior to the maximum number of iterations either when the weight of the syndrome is zero, or when the current number of iterations reaches an iteration number threshold and the weight of the syndrome equals or exceeds a checksum threshold.

3. 发明申请

US20180262211A1 STOPPING CRITERION FOR DECODING QUASI-CYCLIC LDPC CODES 审中-公开
公开(公告)号：US20180262211A1
公开(公告)日：2018-09-13
申请号：US15913427
申请日：2018-03-06
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , Politechnica University of Timisoara , Ecole Nationale Superieure De L'Electronique Et Applications (ENSEA) , Universite De Cergy Pontoise
发明人： Valentin SAVIN , Oana Boncalo , David Declercq
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/1128 , H03M13/1105 , H03M13/1111 , H03M13/114 , H03M13/116 , H03M13/616 , H03M13/6502 , H04L1/0051 , H04L1/0057
摘要： An in-between layer partial syndrome stopping (IBL-PS) criterion for a layered LDPC decoder. The IBL-PS syndrome is obtained by applying the parity checks (Hr,r+1) of a couple of a first layer (r) and a second layer (r+1) on the variables after the first layer has been processed and before the second layer is processed by the decoder, the decoding being stopped if said in-between layer syndrome (sr,r+1) is satisfied for at least a couple of consecutive layers.

4. 发明授权

US09973973B2 Signal processing devices and methods 有权
公开(公告)号：US09973973B2
公开(公告)日：2018-05-15
申请号：US15244183
申请日：2016-08-23
申请人： MediaTek Singapore Pte. Ltd.
发明人： Jiye Liang , Wei-De Wu , Jinghu Chen , Chia-Wei Tai , Hsiang Sheng Hu
IPC分类号： H04W28/22 , H04L5/00 , H04W72/04 , H04W24/08
CPC分类号： H04W28/22 , H04L1/00 , H04L1/0051 , H04L1/0061 , H04L1/0067 , H04L1/0073 , H04L1/203 , H04L5/00 , H04W24/08 , H04W72/042
摘要： A signal processing device for communication is provided and includes a de-rate matching module, a decoder, a signal-quality generation module, and a first control module. The de-rate matching module performs a de-rate matching operation on the control signal to obtain a de-rate matching signal. The decoder performs a decoding operation on the de-rate matching signal to obtain a decoding signal. The signal-quality generation module generates at least one signal-quality indicator according to the control signal and the de-rate matching signal. The at least one signal-quality indicator includes a similarity indictor which is obtained by the signal-quality generation module performing a similarity calculation operation on the control signal and the de-rate matching signal. The first control module determines and controls whether to stop the decoding operation for the de-rate matching signal of the current control signal according to the at least one signal-quality indicator.

5. 发明授权

US09843414B2 Low complexity error correction 有权
公开(公告)号：US09843414B2
公开(公告)日：2017-12-12
申请号：US14788150
申请日：2015-06-30
申请人： Chris Winstead , Gopalakrishnan Sundararajan , Emmanuel Boutillon
发明人： Chris Winstead , Gopalakrishnan Sundararajan , Emmanuel Boutillon
IPC分类号： G06F11/10 , H04L1/00 , H03M13/43 , H03M13/35
CPC分类号： H04L1/0063 , H03M13/1108 , H03M13/353 , H03M13/3723 , H03M13/43 , H04L1/0051 , H04L1/0057
摘要： For low complexity error correction, a decoder modifies each reliability metric of an input data stream with a random perturbation value. The reliability metric comprises a weighted sum of a channel measurement for the input data stream and parity check results for the input data stream. In addition, the decoder may generate an output data stream as a function of the reliability metrics.

6. 发明申请

US20170264316A1 APPARATUS AND METHOD FOR RECEIVING SIGNAL IN COMMUNICATION SYSTEM SUPPORTING LOW DENSITY PARITY CHECK CODE 审中-公开
公开(公告)号：US20170264316A1
公开(公告)日：2017-09-14
申请号：US15456315
申请日：2017-03-10
申请人： Samsung Electronics Co., Ltd. , KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
发明人： Myeong-Woo Lee , Young-Kil Suh , Jun Heo , Jong-Hyun Baik
IPC分类号： H03M13/11 , H04L1/20 , H04L1/00
CPC分类号： H03M13/1125 , H04L1/0051 , H04L1/0053 , H04L1/0057 , H04L1/0061 , H04L1/20
摘要： The present disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system such as a long term evolution (LTE). A method of a receiving apparatus in a communication system supporting a low density parity check (LDPC) code is provided. The method includes deactivating variable nodes of which absolute values of log likelihood ratio (LLR) values are greater than or equal to a first threshold value; changing LLR values of variable nodes of which absolute values of LLR values are less than a second threshold value among variable nodes other than the deactivated variable nodes to a preset value, and detecting LLR values of check nodes based on LLR values of the variable nodes other than the deactivated variable nodes.

7. 发明申请

US20160344419A1 TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF 有权
公开(公告)号：US20160344419A1
公开(公告)日：2016-11-24
申请号：US14716093
申请日：2015-05-19
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Se-ho MYUNG , Hong-sil JEONG , Kyung-joong KIM
IPC分类号： H03M13/27 , H03M13/11 , H03M13/00 , H04L1/00
CPC分类号： H03M13/1165 , H03M13/1148 , H03M13/152 , H03M13/255 , H03M13/271 , H03M13/2732 , H03M13/2778 , H03M13/2792 , H03M13/2906 , H03M13/616 , H04L1/0041 , H04L1/0045 , H04L1/005 , H04L1/0051 , H04L1/0057 , H04L1/0058 , H04L1/0071
摘要： A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

8. 发明申请

US20160336964A1 SYSTEMS AND METHODS FOR EARLY EXIT OF LAYERED LDPC DECODER 有权
标题翻译：早期退出LDPC解码器的系统和方法
公开(公告)号：US20160336964A1
公开(公告)日：2016-11-17
申请号：US14708507
申请日：2015-05-11
申请人： JMicron Technology Corporation
发明人： Mohammad Athar Khalil , Shirley Xiaoling Fang , Jimmy Pu
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/114 , H03M13/1128 , H03M13/116 , H04L1/0051 , H04L1/0057
摘要： The present invention provides systems and methods to detect when hard decisions change for bit nodes of one or more layers of a layered LDPC decoder and to update accumulated partial syndrome calculations for those layers. As hard decisions of bit nodes are generated, they are compared with their previous values. If the hard decisions change, partial syndrome calculations are accumulated and updated for the layers having non-zero elements in one or more columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions. If the hard decisions for the bit nodes are unchanged, the partial syndrome calculations for the corresponding layers are not updated. Changes to hard decisions of codewords are tracked and partial syndromes are flipped for the layers of the columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions.
摘要翻译：本发明提供了用于检测何时硬判决对分层LDPC解码器的一层或多层的位节点改变并且更新那些层的累积部分校正子计算的系统和方法。当生成位节点的硬判决时，将它们与之前的值进行比较。如果硬判决改变，则对于与改变的硬判决的比特节点相对应的奇偶校验矩阵的一个或多个列中的具有非零元素的层，累积和更新部分校正子计算。如果位节点的硬判决不变，则不更新相应层的部分校正子计算。跟踪对码字的硬判决的改变，并且针对对应于改变的硬判决的比特节点的奇偶校验矩阵的列的层翻转部分综合。

9. 发明授权

US09319180B2 Partitioning forward error correction decoding iterations to accommodate multiple data streams 有权
标题翻译：分离前向纠错解码迭代以适应多个数据流
公开(公告)号：US09319180B2
公开(公告)日：2016-04-19
申请号：US14319354
申请日：2014-06-30
申请人： Infinera Corporation
发明人： Sandy Thomson , Han Sun , John D. McNicol
IPC分类号： H03M13/00 , H04L1/00 , H03M13/29
CPC分类号： H04L1/0045 , H03M13/2957 , H03M13/2987 , H03M13/3746 , H03M13/3761 , H03M13/6306 , H04B10/60 , H04J14/02 , H04L1/0051 , H04L1/0052 , H04L1/0057
摘要： An optical receiver may receive a data stream, and may decode the data stream using a first iterative forward error correction (FEC) decoder. The optical receiver may determine whether to further decode the data stream using the first iterative FEC decoder or a second iterative FEC decoder that is different from the first iterative FEC decoder. The optical receiver may selectively perform a first action or a section action based on determining whether to further decode the data stream. The first action may include providing the data stream to the first iterative FEC decoder or the second iterative FEC decoder for further decoding when the data stream is to be further decoded. The second action may include preventing the data stream from being provided to the first iterative FEC decoder or the second iterative FEC decoder when the data stream is not to be further decoded.
摘要翻译：光接收机可以接收数据流，并且可以使用第一迭代前向纠错（FEC）解码器对数据流进行解码。光接收机可以使用不同于第一迭代FEC解码器的第一迭代FEC解码器或第二迭代FEC解码器来确定是否进一步解码数据流。光接收机可以基于确定是否进一步解码数据流来选择性地执行第一动作或片段动作。第一动作可以包括将数据流提供给第一迭代FEC解码器或第二迭代FEC解码器，用于在要进一步解码数据流时进一步解码。第二动作可以包括当数据流不被进一步解码时，防止数据流被提供给第一迭代FEC解码器或第二迭代FEC解码器。

10. 发明申请

US20150311919A1 CODE DESIGN AND HIGH-THROUGHPUT DECODER ARCHITECTURE FOR LAYERED DECODING OF A LOW-DENSITY PARITY-CHECK CODE 有权
标题翻译：用于低密度奇偶校验代码的层次解码的代码设计和高速解码器架构
公开(公告)号：US20150311919A1
公开(公告)日：2015-10-29
申请号：US14323635
申请日：2014-07-03
申请人： Infinera Corporation
发明人： Mehdi KARIMI , Han SUN , Yuejian WU , Scott G. PRINGLE , Sandy THOMSON
IPC分类号： H03M13/11 , H04L1/00
CPC分类号： H03M13/1128 , H03M13/1134 , H03M13/114 , H03M13/1154 , H03M13/116 , H04L1/005 , H04L1/0051 , H04L1/0057
摘要： A low-density parity-check (LDPC) decoder may receive LDPC coded data. The LDPC decoder may perform a decoding iteration associated with decoding the LDPC coded data. The decoding iteration may be performed by processing a group of layers. Each layer may include a corresponding set of check node elements, and may be processed by causing each check node element, of the set of check node elements corresponding to the layer, to update a set of variable node elements, connected to the check node element and associated with the LDPC coded data, based on a check node function associated with the check node element. The decoding iteration may be performed such that each layer is processed in parallel, and such that each check node element updates the corresponding set of variable node elements in parallel. The LDPC decoder may provide a result of performing the decoding iteration.
摘要翻译：低密度奇偶校验（LDPC）解码器可以接收LDPC编码数据。 LDPC解码器可以执行与解码LDPC编码数据相关联的解码迭代。解码迭代可以通过处理一组层来执行。每个层可以包括对应的一组校验节点元素，并且可以通过使与该层相对应的校验节点元素组的每个校验节点元素来更新连接到校验节点元素的一组变量节点元素并且基于与所述校验节点元素相关联的校验节点功能与所述LDPC编码数据相关联。可以执行解码迭代，使得每个层被并行处理，并且使得每个校验节点元素并行地更新相应的变量节点元素组。 LDPC解码器可以提供执行解码迭代的结果。

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