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1. 发明授权

US09715269B2 Platform communication protocol 有权
公开(公告)号：US09715269B2
公开(公告)日：2017-07-25
申请号：US14583333
申请日：2014-12-26
申请人： Intel Corporation
发明人： Seh W. Kwa , Neil Songer , Rob Gough , David J. Harriman
IPC分类号： G06F1/00 , G06F1/32 , G06F13/42 , G06F13/24
CPC分类号： G06F1/324 , G06F1/3209 , G06F13/24 , G06F13/4221 , G06F13/4265 , Y02B60/1235 , Y02D10/151
摘要： A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

2. 发明申请

US20150127874A1 PLATFORM COMMUNICATION PROTOCOL 审中-公开
标题翻译： “平台通信协议”
公开(公告)号：US20150127874A1
公开(公告)日：2015-05-07
申请号：US14583333
申请日：2014-12-26
申请人： Intel Corporation
发明人： Seh W. Kwa , Neil Songer , Rob Gough , David J. Harriman
IPC分类号： G06F1/32 , G06F13/24 , G06F13/42
CPC分类号： G06F1/324 , G06F1/3209 , G06F13/24 , G06F13/4221 , G06F13/4265 , Y02B60/1235 , Y02D10/151
摘要： A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.
摘要翻译：在一些实施例中，可以利用主机芯片组心跳来在功率有效的基础上处理来自外部设备的中断。主机芯片组心跳的可用性可以被发送到外部设备，并且那些外部设备可以将其活动的时间延长到不仅资源可用的时间段，而且活动的断言是有利的，因为主机芯片组已经从降低功耗状态。

3. 发明授权

US6157688A Signal transmission system for transmitting signals between LSI chips, receiver circuit for use in the signal transmission system, and semiconductor memory device applying the signal transmission system 失效
公开(公告)号：US6157688A
公开(公告)日：2000-12-05
申请号：US944516
申请日：1997-10-06
申请人： Hirotaka Tamura , Miyoshi Saito , Kohtaroh Gotoh , Shigetoshi Wakayama , Junji Ogawa , Hisakatsu Araki , Tsz-shing Cheung
发明人： Hirotaka Tamura , Miyoshi Saito , Kohtaroh Gotoh , Shigetoshi Wakayama , Junji Ogawa , Hisakatsu Araki , Tsz-shing Cheung
IPC分类号： G06F3/00 , G06F1/10 , G06F12/00 , G06F13/16 , G06F13/42 , G11C11/401 , G11C11/407 , G11C11/409 , H04B14/06 , G11C16/06
CPC分类号： H04L25/0276 , G06F13/4243 , H04L25/0278 , H04L25/0282 , H04L25/0288 , H04L25/497 , Y02B60/1228 , Y02B60/1235
摘要： A signal transmission system has a response time of a signal transmission line which is set approximately equal to or longer than the length of a transmitted symbol. More specifically, terminal resistance is set larger than the characteristic impedance of the signal transmission line, driver output resistance is set to a large value, or a damping resistor is provided in series with the signal transmission line. With this configuration, signal power can be reduced drastically.

4. 发明授权

US6131132A High performance peripheral interface 失效
标题翻译：高性能外设接口
公开(公告)号：US6131132A
公开(公告)日：2000-10-10
申请号：US459561
申请日：1995-06-02
申请人： Kenneth C. Curt , Edward J. Chejlava, Jr. , Anthony Kozaczuk
发明人： Kenneth C. Curt , Edward J. Chejlava, Jr. , Anthony Kozaczuk
IPC分类号： G06F13/12 , G06F3/06 , G06F13/36 , G06F13/38 , G06F13/00
CPC分类号： G06F3/0601 , G06F13/385 , G06F3/061 , G06F3/0656 , G06F3/0689 , G06F2003/0692 , G06F3/0638 , Y02B60/1228 , Y02B60/1235
摘要： A high performance peripheral interface device is coupled to a computer via a computer bus and is coupled to a peripheral via a peripheral bus. To speed accessing of consecutively addressed data (the nth datum and the n+1th datum) from the peripheral, the interface device reads the n+1th datum from the peripheral: 1) before the computer has requested the n+1th datum from the interface device, and 2) while the computer is accessing the nth datum from the interface device.
摘要翻译：高性能外围接口设备经由计算机总线耦合到计算机，并通过外围总线耦合到外围设备。为了加速从外设访问连续寻址的数据（第n个数据和第n + 1个数据），接口设备从外设读取第n + 1个数据：1）在计算机从接口请求第n + 1个数据之前设备，2）当计算机从接口设备访问第n个数据时。

5. 发明授权

US6125414A Terminating apparatus adapted to terminate single ended small computer system interface (SCSI) devices, low voltage differential SCSI devices, or high voltage differential SCSI devices 失效
标题翻译：适用于终止单端小型计算机系统接口（SCSI）设备，低压差分SCSI设备或高压差分SCSI设备的终端设备
公开(公告)号：US6125414A
公开(公告)日：2000-09-26
申请号：US103199
申请日：1998-06-23
申请人： Abbas Ali
发明人： Abbas Ali
IPC分类号： G06F13/40 , H03K17/16 , G06F13/00
CPC分类号： G06F13/4086 , Y02B60/1228 , Y02B60/1235
摘要： A terminating apparatus adapted to terminate a parallel small computer system interface (SCSI) disc drive or device is disclosed. The terminating apparatus includes termination circuitry adapted to terminate data/control lines of single ended (SE) SCSI devices, low voltage differential (LVD) SCSI devices and high voltage differential (HVD) SCSI devices. The terminating apparatus also includes a first connector coupled to the termination circuitry and adapted to be coupled to data/control lines of the SCSI device to be terminated through the disc drive connector.
摘要翻译：公开了适于终止并行小型计算机系统接口（SCSI）盘驱动器或设备的终端设备。终端设备包括适于终止单端（SE）SCSI设备，低电压差分（LVD）SCSI设备和高电压差分（HVD）SCSI设备的数据/控制线）的终端电路。终端设备还包括耦合到终端电路的第一连接器，并且适于耦合到要通过盘驱动器连接器端接的SCSI设备的数据/控制线。

6. 发明授权

US6122746A System for powering up and powering down a server 失效
标题翻译：为服务器上电和关机的系统
公开(公告)号：US6122746A
公开(公告)日：2000-09-19
申请号：US943076
申请日：1997-10-01
申请人： Ahmad Nouri , Karl S. Johnson
发明人： Ahmad Nouri , Karl S. Johnson
IPC分类号： G06F1/00 , G06F1/20 , G06F1/26 , G06F3/06 , G06F9/445 , G06F11/07 , G06F11/273 , G06F11/30 , G06F11/32 , G06F11/34 , G06F13/40 , G06F21/00 , H04L12/12 , H04L12/24 , H04L12/26 , H04L12/40 , H04L12/56 , H05K7/20 , G06F1/32
CPC分类号： H04L43/065 , G06F1/20 , G06F1/206 , G06F1/26 , G06F11/0748 , G06F11/0775 , G06F11/2294 , G06F11/3006 , G06F11/3058 , G06F11/3065 , G06F11/328 , G06F11/3466 , G06F13/4027 , G06F21/305 , G06F21/31 , G06F9/4411 , H04L12/12 , H04L41/12 , H04L41/22 , G06F11/0793 , G06F11/3476 , G06F11/3495 , G06F2003/0692 , G06F2201/86 , G06F3/0601 , H04L41/0213 , H04L43/045 , H04L43/0817 , H04L43/0823 , H04L43/106 , H04L43/16 , Y02B60/1228 , Y02B60/1235 , Y02B60/1275 , Y02B60/165 , Y02B60/32 , Y02B60/34
摘要： A fault tolerant computer system for powering up and powering down a server through either a local or remote client machine. The remote machine accesses the server by use of a dial-in modem connection. The power up operation brings the server to an operational state such that diagnostics or recovery can be performed even though the operating system software on the server is not operational. Power down is used when diagnosis and maintenance, such as changing a part, needs to be done. Other reasons for power down are for security or power conservation.
摘要翻译：容错计算机系统，用于通过本地或远程客户端机器为服务器上电和关机。远程机器通过使用拨入式调制解调器连接访问服务器。上电操作使服务器处于运行状态，即使服务器上的操作系统软件不可操作，也可执行诊断或恢复。需要进行诊断和维护（如更换部件）时，可以使用掉电。断电的其他原因是为了安全或节能。

7. 发明授权

US6079024A Bus interface unit having selectively enabled buffers 失效
标题翻译：总线接口单元具有有选择地使能的缓冲器
公开(公告)号：US6079024A
公开(公告)日：2000-06-20
申请号：US954040
申请日：1997-10-20
申请人： Massoud Hadjimohammadi , Sunil K. Asthana
发明人： Massoud Hadjimohammadi , Sunil K. Asthana
IPC分类号： G06F13/40 , G06F1/32
CPC分类号： G06F13/4072 , Y02B60/1228 , Y02B60/1235
摘要： A computer system includes a bus interface with a plurality of data buffers. Each data buffer is clocked by an individual clock signal. To reduce the power consumption of the bus interface unit, the clock signals of the data buffers that are inactive are disabled during the period of inactivity. The bus interface unit includes a clock control unit that monitors a data bus coupled to the bus interface to determine when a bus cycle begins and the type of bus cycle. The clock control unit additionally monitors memory and CPU buffer signals that indicate which, if any, buffers are being accessed by the memory or CPU. From this information, the clock control unit determines which buffers are active and inactive, and outputs control signals to a clock unit to disable the clock signals associated with inactive buffers.
摘要翻译：计算机系统包括具有多个数据缓冲器的总线接口。每个数据缓冲器由单独的时钟信号计时。为了降低总线接口单元的功耗，在不活动期间禁用的数据缓冲器的时钟信号被禁止。总线接口单元包括时钟控制单元，其监视耦合到总线接口的数据总线以确定总线周期何时开始以及总线周期的类型。时钟控制单元另外监视存储器和CPU缓冲器信号，该信号指示存储器或CPU正在访问缓冲器（如果有的话）。根据该信息，时钟控制单元确定哪些缓冲器是有效和无效的，并且将控制信号输出到时钟单元以禁用与非活动缓冲器相关联的时钟信号。

8. 发明授权

US6065075A I/O port signal conversion apparatus and method 失效
标题翻译： I / O口信号转换装置及方法
公开(公告)号：US6065075A
公开(公告)日：2000-05-16
申请号：US61828
申请日：1998-04-16
申请人： John Van Ryzin , Adrian Parvulescu
发明人： John Van Ryzin , Adrian Parvulescu
IPC分类号： G06F13/00
CPC分类号： G06F13/4068 , Y02B60/1228 , Y02B60/1235
摘要： I/O port signal conversion apparatus for converting between I/O port signals of a first voltage level coupled from or supplied to an I/O port of a computer and A1 signals of a second voltage level supplied to or coupled from audio/video equipment arranged in an S-LINK cable bus system with an S-LINK cable bus. The computer inserts into the I/O port signals audio/video equipment headers that flag respective audio/video equipment which poll the S-LINK cable bus. A plug couples the I/O port signals and the A1 signals between the I/O port and the S-LINK cable bus system. A voltage control circuit disposed within the plug converts between the voltage level of the I/O port signals and the voltage level of the A1 signals.
摘要翻译：用于在从计算机的I / O端口耦合或提供给计算机的I / O端口的第一电压电平的I / O端口信号和提供给或耦合到音频/视频设备的第二电压电平的A1信号之间进行转换的I / O端口信号转换装置安装在带有S-LINK电缆总线的S-LINK电缆总线系统中。计算机插入I / O端口信号音频/视频设备标题，用于标记轮询S-LINK电缆总线的相应音频/视频设备。一个插头将I / O端口信号和A1信号耦合在I / O端口和S-LINK电缆总线系统之间。设置在插头内的电压控制电路在I / O端口信号的电压电平和A1信号的电压电平之间转换。

9. 发明授权

US6064626A Peripheral buses for integrated circuit 失效
标题翻译：集成电路外围总线
公开(公告)号：US6064626A
公开(公告)日：2000-05-16
申请号：US127605
申请日：1998-07-31
申请人： Ashley Miles Stevens
发明人： Ashley Miles Stevens
IPC分类号： G06F13/40 , G11C13/00
CPC分类号： G06F13/405 , Y02B60/1228 , Y02B60/1235
摘要： The present invention provides an integrated circuit comprising a system bus to which a processor is connectable, and first and second peripheral buses to which peripheral units used by said processor are connected, the first peripheral bus operating at a higher clock speed than the second peripheral bus. Further, the integrated circuit comprises bridge logic for providing an interface between the system bus and the peripheral buses to enable signals to be passed between the system bus and the peripheral buses, the bridge logic comprising clock resynchronisation logic for synchronising the system bus and the peripheral buses.Through the provision of first and second peripheral buses operating at different clock speeds, the integrated circuit of the present invention provides a great deal of flexibility for reducing the power consumption of the integrated circuit as compared with a similar integrated circuit having only one peripheral bus. Since the power consumption of each peripheral bus is proportional to the clock frequency and capacitance, significant power consumption savings can be realised by ensuring that each peripheral unit is connected to the slowest peripheral bus appropriate for that peripheral unit.
摘要翻译：本发明提供了一种集成电路，其包括可连接处理器的系统总线，以及由所述处理器使用的外围单元连接到的第一和第二外围总线，所述第一外围总线以比所述第二外部总线更高的时钟速度工作。此外，集成电路包括用于在系统总线和外围总线之间提供接口的桥逻辑，以使信号能够在系统总线和外围总线之间通过，该桥逻辑包括用于同步系统总线和外设的时钟再同步逻辑巴士通过提供以不同时钟速度工作的第一和第二外围总线，与仅具有一个外围总线的类似集成电路相比，本发明的集成电路提供了大大降低集成电路的功耗的灵活性。由于每个外设总线的功耗与时钟频率和电容成正比，所以通过确保每个外围设备连接到适合该外设的最慢的外设总线，可以节省大量的功耗。

10. 发明授权

US6055581A Vital product data concentrator and protocol converter 失效
标题翻译：重要的产品数据集中器和协议转换器
公开(公告)号：US6055581A
公开(公告)日：2000-04-25
申请号：US912403
申请日：1997-08-18
申请人： Neil Clair Berglund , Todd Jon Rosedahl
发明人： Neil Clair Berglund , Todd Jon Rosedahl
IPC分类号： G06F15/02
CPC分类号： G06F13/387 , Y02B60/1228 , Y02B60/1235
摘要： A concentrator and protocol converter for concentrating signals from a plurality of information circuits and coupling to a computer system control device, and for converting between at least two communications protocols. The information circuits contain vital product data (VPD) about associated devices which is used by the computer system control device.
摘要翻译：一种集中器和协议转换器，用于集中来自多个信息电路的信号并耦合到计算机系统控制设备，并用于在至少两个通信协议之间进行转换。信息电路包含关于由计算机系统控制设备使用的关联设备的关键产品数据（VPD）。

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