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1. 发明授权

US09915002B2 System and method for producing a nano metal mesh using a brittle film template for lithography 有权
公开(公告)号：US09915002B2
公开(公告)日：2018-03-13
申请号：US14860582
申请日：2015-09-21
申请人： Ethan Pfeiffer
发明人： Ethan Pfeiffer
IPC分类号： C23F1/16 , B81C1/00 , H01L21/033 , B82Y40/00
CPC分类号： G06F3/044 , B81C1/00476 , B82Y40/00 , C23F1/16 , G06F2203/04103 , H01L21/0331 , Y10S148/10 , Y10S977/856 , Y10S977/857 , Y10S977/893
摘要： This disclosure teaches a method for producing a nano metal mesh. A brittle layer can be deposited onto a flexible substrate, the brittle layer having a thickness on the flexible substrate. The flexible substrate can be bent to produce a plurality of gaps on the brittle material. A material can be deposited at the surface of the flexible substrate filling the gaps of the brittle layer. Then, the brittle layer can be etched from the flexible substrate using an etchant, a nano metal mesh formed by the material previously in the gaps. The disclosure also teaches a nano metal mesh made using this method.

2. 发明授权

US5856232A Method for fabricating T-shaped electrode and metal layer having low resistance 失效
标题翻译：用于制造具有低电阻的T形电极和金属层的方法
公开(公告)号：US5856232A
公开(公告)日：1999-01-05
申请号：US675972
申请日：1996-07-05
申请人： Jeon-Wook Yang , Eung-Gee Oh , Byung-Sun Park , Chul-Sun Park , Kwang-Eui Pyun
发明人： Jeon-Wook Yang , Eung-Gee Oh , Byung-Sun Park , Chul-Sun Park , Kwang-Eui Pyun
IPC分类号： H01L21/28 , H01L21/285 , H01L21/338 , H01L29/41 , H01L29/812
CPC分类号： H01L21/28587 , H01L21/28581 , Y10S148/10
摘要： A method for fabricating a T-shaped gate electrode includes the steps of: forming a fine gate pattern on a semiconductor substrate; forming an insulating layer on the semiconductor substrate on which the gate pattern is formed, and forming a planarizing layer on the insulating layer to planarize the surface of the semiconductor substrate; etching the planarizing layer to expose the top of the insulating layer; isotropically etching the insulating layer to expose the gate pattern using the planarizing layer as a mask; etching the exposed gate pattern to selectively expose the semiconductor substrate; depositing a gate metal to cover the exposed substrate, the insulating layer and the planarizing layer, to form a T-shaped gate; and simultaneously removing the planarizing layer, thereby forming a T-shaped gate metal with improved productivity.
摘要翻译：一种制造T形栅电极的方法包括以下步骤：在半导体衬底上形成精细栅极图案; 在其上形成有栅极图案的半导体衬底上形成绝缘层，并在绝缘层上形成平坦化层以使半导体衬底的表面平坦化; 蚀刻平坦化层以暴露绝缘层的顶部; 使用平坦化层作为掩模，各向同性蚀刻绝缘层以露出栅极图案; 蚀刻暴露的栅极图案以选择性地暴露半导体衬底; 沉积栅极金属以覆盖暴露的基板，绝缘层和平坦化层，以形成T形门; 同时除去平坦化层，从而形成T形门金属，生产率提高。

3. 发明授权

US5587328A Method for manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5587328A
公开(公告)日：1996-12-24
申请号：US572876
申请日：1995-12-18
申请人： Kazuhiro Yoshida
发明人： Kazuhiro Yoshida
IPC分类号： H01L29/812 , H01L21/027 , H01L21/285 , H01L21/338 , H01L21/265
CPC分类号： H01L29/66863 , H01L21/0272 , H01L21/28587 , Y10S148/10 , Y10S438/948
摘要： A semiconductor device manufacturing method with which a GaAs MESFET and an integrated circuit using the same can be manufactured cheaply and with high yield by accurately forming a mushroom-shaped gate electrode with inexpensive equipment and a short process. The method includes the steps of: depositing a first mask layer on a semiconductor substrate; forming an opening in the first mask layer; causing the first mask layer to flow by heat-treating the semiconductor substrate; depositing a second mask layer on the first mask layer; forming in the second mask layer an opening larger than the opening in the first mask layer and exposing the opening in the first mask layer; and forming a gate electrode in the opening in the second mask layer.
摘要翻译：通过使用便宜的设备和短的工艺精确地形成蘑菇形栅电极，可以廉价地制造GaAs MESFET和使用其的集成电路的半导体器件制造方法。该方法包括以下步骤：在半导体衬底上沉积第一掩模层; 在所述第一掩模层中形成开口; 通过热处理半导体衬底使第一掩模层流动; 在所述第一掩模层上沉积第二掩模层; 在所述第二掩模层中形成大于所述第一掩模层中的开口的开口并暴露所述第一掩模层中的所述开口; 以及在第二掩模层的开口中形成栅电极。

4. 发明授权

US5550405A Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS 失效
标题翻译：用于实现生产有价值，低电介质，低互连电阻和高性能ICS的加工技术
公开(公告)号：US5550405A
公开(公告)日：1996-08-27
申请号：US360856
申请日：1994-12-21
申请人： Robin W. Cheung , Mark S. Chang
发明人： Robin W. Cheung , Mark S. Chang
IPC分类号： H01L21/28 , H01L21/027 , H01L21/768 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53242 , H01L23/53228 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L2924/0002 , Y10S148/10 , Y10S148/106 , Y10S438/95 , Y10S438/951
摘要： The interconnects in a semiconductor device contacting metal lines comprise a low resistance metal, such as copper, gold, silver, or platinum, and are separated by a material having a low dielectric constant, such as benzocyclobutene or a derivative thereof. A tri-layer resist structure is used, together with a lift-off process, to form the interconnects. The low dielectric constant material provides a diffusion barrier to the diffusion of the low resistance metal. The tri-layer resist comprises a first layer of a dissolvable polymer, a second layer of a hard mask material, and a third layer of a resist material. The resulting structure provides an integrated circuit with increased speed and ease of fabrication.
摘要翻译：接触金属线的半导体器件中的互连包括诸如铜，金，银或铂的低电阻金属，并且由具有低介电常数的材料例如苯并环丁烯或其衍生物分离。使用三层抗蚀剂结构以及剥离工艺来形成互连。低介电常数材料为低电阻金属的扩散提供扩散阻挡层。三层抗蚀剂包括可溶解聚合物的第一层，硬掩模材料的第二层和抗蚀剂材料的第三层。所得到的结构提供了具有增加的速度和易于制造的集成电路。

5. 发明授权

US5541444A Device and method of manufacturing the same and semiconductor device and method of manufacturing the same 失效
标题翻译：其制造方法及其制造方法及其制造方法
公开(公告)号：US5541444A
公开(公告)日：1996-07-30
申请号：US304219
申请日：1994-09-12
申请人： Tadahiro Ohmi , Mamoru Miyawaki
发明人： Tadahiro Ohmi , Mamoru Miyawaki
IPC分类号： H01L29/73 , H01L21/283 , H01L21/316 , H01L21/331 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/737 , H01L29/78 , A01L27/082
CPC分类号： H01L29/66287 , H01L21/31683 , H01L29/0847 , H01L29/1033 , H01L29/41775 , H01L29/42304 , H01L29/66272 , H01L29/66545 , H01L29/66613 , H01L29/66628 , H01L29/7375 , H01L29/7378 , H01L2924/0002 , Y10S148/10 , Y10S438/926 , Y10S438/951
摘要： A device having, at least, a first film having a surface on which neither a natural oxide film nor impurity grains caused by a resist residue is or are present, and a conductive material layer formed on a surface adjacent to the surface of the first film, wherein an insulative compound film is formed on a surface of the conductive material layer by a surface reaction with the conductive material layer, and a predetermined second film required for an arrangement is formed on the surface of the first film.
摘要翻译：一种具有至少具有其表面上没有自然氧化物膜和由抗蚀剂残渣引起的杂质颗粒的表面的第一膜的器件，以及形成在与第一膜的表面相邻的表面上的导电材料层其中通过与导电材料层的表面反应在导电材料层的表面上形成绝缘化合物膜，并且在第一膜的表面上形成预定的第二膜。

6. 发明授权

US5541128A Self-aligned thin-film transistor constructed using lift-off technique 失效
标题翻译：使用剥离技术构建的自对准薄膜晶体管
公开(公告)号：US5541128A
公开(公告)日：1996-07-30
申请号：US533406
申请日：1995-09-25
申请人： Robert F. Kwasnick , George E. Possin
发明人： Robert F. Kwasnick , George E. Possin
IPC分类号： H01L29/78 , H01L21/033 , H01L21/336 , H01L29/786 , H01L21/86
CPC分类号： H01L29/78696 , H01L21/0331 , H01L29/66765 , H01L29/78669 , Y10S148/10 , Y10S438/951
摘要： In the fabrication of thin-film field-effect transistors, a dielectric island is first formed over a gate and between locations where source and drain contacts are to be deposited. A dielectric cap with an overhanging brim is formed on the island. A layer of SD metal which will form the source-drain contacts is next deposited. Because of the overhang, the SD metal does not coat the entire cap, but leaves part of the cap remaining exposed and attackable by an etchant. Application of an etchant etches away the island and the cap, thereby lifting off the SD metal coated on the cap, leaving the fully-formed source and drain contacts in place, separated by the extent of the island.
摘要翻译：在薄膜场效应晶体管的制造中，电介质岛首先形成在栅极上以及在源极和漏极接触物将被沉积的位置之间。在岛上形成具有突出边缘的电介质盖。接下来沉积将形成源极 - 漏极触点的SD金属层。由于悬垂，SD金属不覆盖整个盖子，而是使盖子的一部分保持暴露并被腐蚀剂侵袭。蚀刻剂的应用蚀刻掉岛和盖，从而剥离涂覆在盖上的SD金属，使得完全形成的源极和漏极触点留在适当位置，由岛的范围分开。

7. 发明授权

US5393696A Method for forming multilayer indium bump contacts 失效
标题翻译：用于形成多层铟凸块接触的方法
公开(公告)号：US5393696A
公开(公告)日：1995-02-28
申请号：US144211
申请日：1993-10-26
申请人： Wei Koh , Wayne D. Kuipers
发明人： Wei Koh , Wayne D. Kuipers
IPC分类号： H01L21/60 , H01L23/485 , H01L4/44
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/13099 , H01L2224/13109 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01033 , H01L2924/01039 , H01L2924/01049 , H01L2924/01077 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , Y10S148/10 , Y10S438/94
摘要： A method for forming multilayer bump contacts for use in flip-chip bump bonding and the like. The method comprises applying a base layer to a substrate and then applying a malleable conductive layer to the base layer. In a first embodiment, individual bump contacts are formed by removing portions of the base layer and malleable layer such that a plurality of bump contacts are formed. In a second embodiment a photoresist and etching process is used. The need to precisely align a mark to define the position of the malleable layer relative to the base layer is eliminated since the positions of the malleable layer and the base layer are defined simultaneously in both embodiments. Thus, the number of process steps is reduced, yield is increased, and alignment accuracy is improved.
摘要翻译：一种形成用于倒装芯片凸块接合等的多层凸块接点的方法。该方法包括将基底层施加到基底上，然后将可延展的导电层施加到基底层。在第一实施例中，通过去除基底层和可延展层的部分以形成多个凸块接触来形成单独的凸起接触。在第二实施例中，使用光致抗蚀剂和蚀刻工艺。由于在两个实施例中同时限定了可塑性层和基层的位置，因此消除了将标记精确对准以限定可延展层相对于基层的位置的需要。因此，处理步骤的数量减少，产量增加，并且对准精度提高。

8. 发明授权

US5223454A Method of manufacturing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5223454A
公开(公告)日：1993-06-29
申请号：US760889
申请日：1991-09-17
申请人： Takayuki Uda , Tasuku Tanaka , Yoshiaki Emoto , Shigeo Kuroda
发明人： Takayuki Uda , Tasuku Tanaka , Yoshiaki Emoto , Shigeo Kuroda
IPC分类号： H01L23/31 , H01L25/065 , H01L25/16
CPC分类号： H01L23/3121 , H01L25/0655 , H01L25/165 , H01L2224/1147 , H01L2224/11472 , H01L2224/11474 , H01L2224/16145 , H01L2224/45124 , H01L2224/48091 , H01L2224/48247 , H01L2224/48472 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01039 , H01L2924/01079 , H01L2924/12032 , H01L2924/1305 , H01L2924/14 , H01L2924/1532 , H01L2924/16152 , H01L2924/181 , H01L2924/19041 , Y10S148/10 , Y10S438/951
摘要： A method of manufacturing a semiconductor integrated circuit device wherein a conductor film is formed on a front surface of a substrate by a lift-off technique; comprising forming a first resist film on that area of the substrate surface on which the conductor film is not formed, forming a second resist film on the whole substrate surface including the first resist film and a conductor film forming area of the substrate surface, providing a first opening for forming the conductor film in a conductor film forming area of the second resist film and also providing a second opening for forming a dummy conductor film in that area of the second resist film in which the conductor film is not formed, depositing the conductor film on the whole substrate surface including the substrate surface inside the first opening, the first resist film inside the second opening and the second resist film, and removing the second resist film and the first resist film respectively, so as to leave the conductor film inside the first opening and to remove the conductor film on the second resist film and the dummy conductor film on the first resist film.
摘要翻译：一种制造半导体集成电路器件的方法，其中通过剥离技术在衬底的前表面上形成导体膜; 包括在其上未形成导体膜的基板表面的区域上形成第一抗蚀剂膜，在包括第一抗蚀剂膜和基板表面的导体膜形成区域的整个基板表面上形成第二抗蚀剂膜，用于在第二抗蚀剂膜的导体膜形成区域中形成导体膜的第一开口，并且还在其中未形成导体膜的第二抗蚀剂膜的区域中提供用于形成虚设导体膜的第二开口，在包括第一开口内的基板表面，第二开口内的第一抗蚀剂膜和第二抗蚀剂膜的整个基板表面上分别去除第二抗蚀剂膜和第一抗蚀剂膜，以便将导体膜留在内部第一开口并且去除第二抗蚀剂膜上的导体膜和第一抗蚀剂膜上的虚设导体膜。

9. 发明授权

US5096846A Method of forming a quantum effect switching device 失效
标题翻译：形成量子效应开关器件的方法
公开(公告)号：US5096846A
公开(公告)日：1992-03-17
申请号：US608406
申请日：1990-11-02
申请人： John N. Randall
发明人： John N. Randall
IPC分类号： H01L21/28 , H01L21/308 , H01L21/335
CPC分类号： B82Y10/00 , H01L21/28 , H01L21/3085 , H01L29/66469 , Y10S148/10 , Y10S438/962
摘要： A method for forming a quantum effect switching device is disclosed which comprises the step of forming a heterostructure substrate 10. A silicon nitride layer 22 is formed on an outer surface of the substrate 10. An aluminum mask body 30 is formed using a lift-off procedure. Aluminum mask body 30 is then used to form a silicon nitride mask body 32 from the silicon nitride layer 22 using a CF.sub.4 /O.sub.2 reactive ion etch process. A boron trichloride etch process is then used to form a dual column structure 34 while removing the aluminum mask body 30. A buffered HF wet etch process removes the silicon nitride mask body 32. Separate metal contacts can then be made to electrically separate points on the outer surface of the dual column structure 34.
摘要翻译：公开了一种用于形成量子效应开关器件的方法，其包括形成异质结构衬底10的步骤。在衬底10的外表面上形成氮化硅层22.铝掩模体30使用剥离程序。然后使用铝掩模体30，使用CF4 / O2反应离子蚀刻工艺从氮化硅层22形成氮化硅掩模体32。然后在去除铝掩模体30的同时，使用三氯化硼蚀刻工艺来形成双重柱结构34.缓冲的HF湿法蚀刻工艺去除氮化硅掩模体32.然后可以将独立的金属接触件电分离在双柱结构34的外表面。

10. 发明授权

US5053348A Fabrication of self-aligned, T-gate HEMT 失效
标题翻译：自对准，T型门HEMT的制造
公开(公告)号：US5053348A
公开(公告)日：1991-10-01
申请号：US444708
申请日：1989-12-01
申请人： Umesh K. Mishra , Mark A. Thompson , Linda M. Jelloian
发明人： Umesh K. Mishra , Mark A. Thompson , Linda M. Jelloian
IPC分类号： H01L29/812 , H01L21/28 , H01L21/285 , H01L21/335 , H01L21/338
CPC分类号： H01L29/66462 , H01L21/28587 , Y10S148/10 , Y10S148/102 , Y10S148/143 , Y10S438/951
摘要： A generally T-shaped gate is formed by electron beam irradiation of a multilevel resist structure on a substrate. The resist structure has an upper layer which is more sensitive to the electron beam than a lower layer thereof. A generally T-shaped opening is formed in the resist structure by etching of the irradiated areas. An electrically conductive metal is deposited to fill the opening and thereby form a T-shaped gate on the substrate. After the resist layer structure and metal deposited thereon is removed, a masking layer is formed on the substrate around the gate, having an opening therethrough which is aligned with and wider than the cross section of the gate, and defining first and second lateral spacings between opposite extremities of the cross section and adjacent edges of the opening. Deposition of an electrically conductive metal forms source and drain metallizations on the substrate on areas underlying the first and lateral spacings respectively. The metallizations are self-aligned to the gate and separated therefrom by the masking effect of the gate during the metal deposition. The gate may have an asymmetrical top section which provides a larger spacing between the gate and drain metallization than between the gate and source metallization to increase the breakdown voltage of the device. Insulative oxide sidewalls may be formed on the gate.

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