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1. 发明申请

US20170048867A1 COMMUNICATION APPARATUS AND COMMUNICATION METHOD FOR INVERSE DISCRETE-FOURIER-TRANSFORMING A FREQUENCY DOMAIN SIGNAL INTO A TIME DOMAIN SYMBOL SEQUENCE 审中-公开
标题翻译：反向离散傅立叶变换将频域信号转换成时域符号序列的通信装置和通信方法
公开(公告)号：US20170048867A1
公开(公告)日：2017-02-16
申请号：US15337985
申请日：2016-10-28
申请人： Sun Patent Trust
发明人： Shinsuke Takaoka , Masayuki Hoshino , Kenichi Miyoshi
IPC分类号： H04W72/04 , H04L27/26
CPC分类号： H04W72/0453 , G06F17/141 , H04J1/00 , H04J4/005 , H04J11/00 , H04L5/0041 , H04L27/2602 , H04L27/2628 , H04L27/2636 , H04W88/08 , Y10S370/916
摘要： A communication apparatus includes a receiver, a combiner, and a transformer. The receiver receives signals mapped on plural frequency bands. A size of at least one of the frequency bands is a multiple of a product of two or more powers of prime numbers, which are integer numbers greater than 1 and are different from each other. An exponent for at least one of the prime numbers is an integer greater than 1. The combiner combines the received signals into a combined signal. The transformer transforms the combined signal in a frequency domain into a symbol sequence in a time domain with an inverse discrete Fourier transform (IDFT) having a size that is a product of powers of plural values. The values are integer numbers greater than 1 and are different from each other. An exponent for at least one of the values is an integer greater than 1.
摘要翻译：通信装置包括接收机，组合器和变压器。接收机接收映射在多个频带上的信号。频带中的至少一个的大小是素数的两个或更多个幂的乘积的倍数，其是大于1并且彼此不同的整数。素数中的至少一个的指数是大于1的整数。组合器将接收到的信号组合成组合信号。变压器将具有尺寸为多值的乘积的反离散傅立叶变换（IDFT）的频域中的组合信号变换为时域中的符号序列。这些值是大于1的整数，彼此不同。至少一个值的指数是大于1的整数。

2. 发明申请

US20140064241A1 COMMUNICATION APPARATUS AND A COMMUNICATION METHOD 有权
标题翻译：通信设备和通信方法
公开(公告)号：US20140064241A1
公开(公告)日：2014-03-06
申请号：US14072668
申请日：2013-11-05
申请人： Panasonic Corporation
发明人： Shinsuke Takaoka , Masayuki Hoshino , Kenichi Miyoshi
IPC分类号： H04L27/26
CPC分类号： H04W72/0453 , G06F17/141 , H04J1/00 , H04J4/005 , H04J11/00 , H04L5/0041 , H04L27/2602 , H04L27/2628 , H04L27/2636 , H04W88/08 , Y10S370/916
摘要： Provided is a radio communication device which can reduce ISI caused by destruction of an orthogonal DFT matrix even when an SC-FDMA signal is divided into a plurality of clusters and the clusters are respectively mapped to discontinuous frequency bands. The radio communication device includes a DFT unit (110), a division unit (111), and a mapping unit (112). The DFT unit (110) uses the DFT matrix to execute a DFT process on a symbol sequence in a time region to generate a signal (SC-FDMA signal) of the frequency region. The division unit (111) generates a plurality of clusters by dividing the SC-FDMA signal with a partially orthogonal bandwidth corresponding to the vector length of some of the column vectors constituting the DFT matrix used in the DFT unit (110) and orthogonally intersecting at least partially. The mapping unit (112) maps the clusters to discontinuous frequency bands.
摘要翻译：提供一种无线电通信装置，即使当SC-FDMA信号被划分为多个群集并且群集分别映射到不连续的频带时，其也可以减少由正交DFT矩阵的破坏引起的ISI。无线通信装置包括DFT单元（110），分割单元（111）和映射单元（112）。 DFT单元（110）使用DFT矩阵对时间区域中的符号序列执行DFT处理，以生成频率区域的信号（SC-FDMA信号）。分割单元（111）通过用对应于构成在DFT单元（110）中使用的DFT矩阵的一些列向量的矢量长度的部分正交带宽划分SC-FDMA信号并且在正交带宽上正交相交最少部分。映射单元（112）将簇映射到不连续的频带。

3. 发明授权

US07739097B2 Emulation system with time-multiplexed interconnect 有权
标题翻译：具有时间复用互连的仿真系统
公开(公告)号：US07739097B2
公开(公告)日：2010-06-15
申请号：US10128178
申请日：2002-04-22
申请人： Stephen P. Sample , Mikhail Bershteyn , Michael R. Butts , Jerry R. Bauer
发明人： Stephen P. Sample , Mikhail Bershteyn , Michael R. Butts , Jerry R. Bauer
IPC分类号： G06F17/50 , H04J99/00 , G06F9/455
CPC分类号： G01R31/2853 , G01R31/31717 , G06F17/5027 , Y10S370/916
摘要： A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.
摘要翻译：公开了一种硬件仿真系统，其通过将多个设计信号时间复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。硬件仿真系统包括多个可重新编程逻辑器件和多个可重新编程的互连器件。逻辑器件和互连器件互连在一起，使得多个设计信号通过使用多路复用共享公共I / O引脚和电路板迹线。

4. 发明授权

US07557783B2 Organic light emitting display 有权
标题翻译：有机发光显示器
公开(公告)号：US07557783B2
公开(公告)日：2009-07-07
申请号：US11227998
申请日：2005-09-14
申请人： Yang Wan Kim
发明人： Yang Wan Kim
IPC分类号： G09G3/32
CPC分类号： G09G3/3233 , G09G3/3291 , G09G2300/0452 , G09G2300/0819 , G09G2300/0842 , G09G2300/0861 , G09G2310/0235 , G09G2310/0297 , G09G2320/043 , Y10S370/916
摘要： An organic light emitting display capable of reducing the manufacturing cost and displaying images with uniform brightness. The organic light emitting display includes: a data driver for supplying a plurality of data signals to a plurality of first data lines, respectively; an image display portion having a plurality of second data lines, a plurality of scan lines, and a plurality of pixels; and a demultiplexer having a plurality of data transistors arranged in the respective first data lines to supply the plurality of data signals supplied to the first data lines to the plurality of second data lines, and a plurality of capacitors connected between respective gate terminals of the plurality of data transistors and the second data lines.
摘要翻译：一种能够降低制造成本并以均匀亮度显示图像的有机发光显示器。有机发光显示器包括：分别将多个数据信号提供给多个第一数据线的数据驱动器; 具有多个第二数据线，多条扫描线和多个像素的图像显示部分; 以及多路分离器，其具有布置在各个第一数据线中的多个数据晶体管，以将提供给第一数据线的多个数据信号提供给多个第二数据线;以及多个电容器，其连接在多个第一数据线的各个栅极端子之间的数据晶体管和第二数据线。

5. 发明申请

US20060075178A1 Communication between logical macros 失效
标题翻译：逻辑宏之间的通信
公开(公告)号：US20060075178A1
公开(公告)日：2006-04-06
申请号：US10958967
申请日：2004-10-05
申请人： Gary Batchelor , Brian Cagno , Renee LaMar , Michael Harper
发明人： Gary Batchelor , Brian Cagno , Renee LaMar , Michael Harper
IPC分类号： G06F13/36
CPC分类号： G06F13/362 , G06F13/4031 , Y10S370/916
摘要： A connection is provided between logical macros to allow prioritization of operations in accordance with an arbitration scheme that distinguishes between operations based on such factors as priority or size of transaction. The invention allows connection of logical macros and prioritizes the appropriate operation for the resources available to optimize data throughput to optimize the utilization of multiple buses. A first arbiter manages data transmissions over a first communication bus. Arriving short or high-priority messages are transmitted over a second communication bus managed by a second arbiter, but only if the target logical macro is not the same as currently targeted by the first arbiter.
摘要翻译：在逻辑宏之间提供连接，以根据基于诸如交易的优先级或大小等因素来区分操作的仲裁方案来确定操作的优先级。本发明允许连接逻辑宏并优先考虑可用于优化数据吞吐量的资源的适当操作，以优化多个总线的利用。第一仲裁器管理通过第一通信总线的数据传输。到达短或高优先级消息通过由第二仲裁器管理的第二通信总线发送，但是仅当目标逻辑宏不同于当前由第一仲裁器定向时。

6. 发明授权

US06732068B2 Memory circuit for use in hardware emulation system 有权
标题翻译：用于硬件仿真系统的存储电路
公开(公告)号：US06732068B2
公开(公告)日：2004-05-04
申请号：US09922113
申请日：2001-08-02
申请人： Stephen P. Sample , Mikhail Bershteyn , Michael R. Butts , Jerry R. Bauer
发明人： Stephen P. Sample , Mikhail Bershteyn , Michael R. Butts , Jerry R. Bauer
IPC分类号： G06F9455
CPC分类号： G01R31/2853 , G01R31/31717 , G06F17/5027 , Y10S370/916
摘要： A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.
摘要翻译：公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板走线。还公开了一种用于硬件仿真系统的逻辑分析仪。执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。

7. 发明申请

US20020052931A1 HTTP multiplexor/demultiplexor 有权
标题翻译： HTTP多路复用器/解复用器
公开(公告)号：US20020052931A1
公开(公告)日：2002-05-02
申请号：US09975522
申请日：2001-10-10
发明人： Christopher Peiffer , Israel L'Heureux
IPC分类号： G06F015/16 , G06F015/173
CPC分类号： H04L29/06 , H04L67/02 , H04L67/142 , H04L67/42 , H04L69/162 , H04L69/165 , Y10S370/916
摘要： A computer networking system, method and device for multiplexing HTTP requests and demultiplexing HTTP responses. The method may include receiving HTTP requests from a plurality of clients and routing those requests to a socket on a server system. The method may also include receiving HTTP responses from the server system and selectively routing those responses to the corresponding clients.
摘要翻译：一种用于复用HTTP请求和解复用HTTP响应的计算机联网系统，方法和设备。该方法可以包括从多个客户端接收HTTP请求并将这些请求路由到服务器系统上的套接字。该方法还可以包括从服务器系统接收HTTP响应并且选择性地将这些响应路由到相应的客户端。

8. 发明授权

US06240274B1 High-speed broadband wireless communication system architecture 失效
标题翻译：高速宽带无线通信系统架构
公开(公告)号：US06240274B1
公开(公告)日：2001-05-29
申请号：US09295705
申请日：1999-04-21
申请人： Hossein Izadpanah
发明人： Hossein Izadpanah
IPC分类号： H04B724
CPC分类号： H04L27/2601 , H04J3/0685 , H04W56/00 , Y10S370/913 , Y10S370/916
摘要： Techniques and architecture as well as channel multiplexing schemes to design and implement multi-megabit and gigabit transfer of data in situations requiring or optimized by wireless communication systems are presented as a method by which the high-speed signal integrity of a transmission may be maintained over a hostile wireless link and by which a high-speed transmission may be made while maintaining a bit-rate below the delay spread value such that the unforgiving propagation conditions normally associated with high-speed transfer are mitigated. The system is adaptable to any use where a multi-megabit and gigabit wireless link is desirable; for example in office buildings lacking fiber infrastructure, in rapid deployment situations such as those required in military or emergency situations, or where other separate broadband infrastructures do not exist to the end users for integrated telephone, Internet, and digital data systems.
摘要翻译：提出了技术和架构以及信道复用方案，用于在由无线通信系统要求或优化的情况下设计和实现数据的多兆位和千兆位传输，作为传输的高速信号完整性可以被维持的方法恶性无线链路，并且可以在保持低于延迟扩展值的比特率的同时进行高速传输，使得通常与高速传输相关联的不原谅的传播条件得到缓解。该系统适用于需要多兆和千兆无线链路的任何用途; 例如在缺乏光纤基础设施的办公楼，在军事或紧急情况下所需的快速部署情况下，或者其他单独的宽带基础设施不存在于终端用户的综合电话，互联网和数字数据系统。

9. 发明授权

US5757801A Advanced priority statistical multiplexer 失效
标题翻译：高级优先级统计多路复用器
公开(公告)号：US5757801A
公开(公告)日：1998-05-26
申请号：US333365
申请日：1994-11-02
申请人： Harinarayana Arimilli
发明人： Harinarayana Arimilli
IPC分类号： H04J3/16 , H04J3/17 , H04J3/24 , H04L12/64 , H04L29/06 , H04M1/253 , H04M11/06 , H04N1/00 , H04J3/00
CPC分类号： H04N1/00281 , H04J3/1688 , H04J3/247 , H04L29/06 , H04M1/253 , H04M11/064 , H04N1/00302 , H04N1/00312 , H04L2012/6427 , H04L2012/6459 , H04L2012/6462 , H04L2012/6464 , H04L2012/6486 , H04L2012/6494 , Y10S370/916
摘要： A data multiplexing network is described which multiplexes a plurality of asynchronous data channels with an asynchronous data stream representing compressed voice signals and/or facsimile signals onto a single synchronous data packet stream. The single synchronous data packet stream is then transmitted by a high speed statistical multiplexer over a composite link to a second site using a modified high-level synchronous data link control protocol with an overlay of an advanced priority statistical multiplexing algorithm. The asynchronous data channels and the compressed voice channel and/or facsimile signals are demultiplexed and reconstructed for sending to other asynchronous computer terminals and to a standard telephone or facsimile analog port at the second site, respectively. PBX trunk interfaces are also provided to allow PBXs to share the composite link between sites. Communication between the first site by voice or facsimile and the second site is transparent to the users. The multiplexer efficiently allocated the bandwidth of the composite link by detecting silence periods in the voice signals and suppressing the sending of the voice information to preserve bandwidth. An advanced priority statistical multiplexer is also described which dynamically allocates composite link bandwidth to both time-sensitive and non-time-sensitive data to maximizes data throughout efficiency and quality while simultaneously reducing multiplexer processing overhead.
摘要翻译：描述了一种数据复用网络，其将多个异步数据信道与表示压缩语音信号和/或传真信号的异步数据流复用到单个同步数据分组流上。然后，使用具有高级优先级统计复用算法的覆盖的经修改的高级同步数据链路控制协议，单个同步数据分组流由高速统计多路复用器通过复合链路发送到第二站点。异步数据信道和压缩语音信道和/或传真信号被解复用和重构，以分别发送到第二站点的其他异步计算机终端和标准电话或传真模拟端口。还提供PBX中继接口，以便PBX共享站点之间的复合链路。第一站点之间通过语音或传真与第二站点之间的通信对于用户来说是透明的。复用器通过检测语音信号中的静音时段，有效地分配复合链路的带宽，抑制语音信息的发送以保持带宽。还描述了一种高级优先级统计复用器，其将复合链路带宽动态地分配给时间敏感和非时间敏感数据，以在效率和质量上最大化数据，同时降低多路复用器处理开销。

10. 发明授权

US5633891A Portable integrated satellite communications unit 失效
标题翻译：便携式综合卫星通信单元
公开(公告)号：US5633891A
公开(公告)日：1997-05-27
申请号：US487509
申请日：1995-08-21
申请人： Mohammed S. Rebec , Mihailo V. Rebec
发明人： Mohammed S. Rebec , Mihailo V. Rebec
IPC分类号： H04B7/185 , H04N7/14 , H04N7/15 , H04N7/20 , H04B1/38
CPC分类号： H04B7/18517 , H04B7/18523 , H04N7/147 , H04N7/15 , H04N7/20 , H04N2007/145 , Y10S370/916
摘要： A high speed teleconferencing apparatus and method, the apparatus including interface means for receiving a first analog signal and outputting a first digital signal, encoding means for encoding and compressing the first digital signal to produce a first compressed encoded signal, multiplexing/demultipexing means for receiving and splitting the first compressed encoded signal into at least two split compressed encoded signals, at least two converting means for receiving a respective one of the at least two split first compressed encoded signals and respectively producing at least two first synchronous signals, and at least two CCIT units for receiving a respective one of the at least tow synchronous signals and respectively outputting at least two high speed first synchronous signals to a high speed data link.
摘要翻译：一种高速电话会议装置和方法，所述装置包括用于接收第一模拟信号并输出第一数字信号的接口装置，用于对第一数字信号进行编码和压缩以产生第一压缩编码信号的编码装置，用于接收的多路复用/解复用装置以及将所述第一压缩编码信号分割为至少两个分离的压缩编码信号，至少两个转换装置，用于接收所述至少两个分离的第一压缩编码信号中的相应一个并分别产生至少两个第一同步信号，以及至少两个 CCIT单元，用于接收所述至少牵引同步信号中的相应一个，并分别向高速数据链路输出至少两个高速第一同步信号。

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