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1. 发明申请

US20230083500A1 STORAGE DEVICE AND OPERATING METHOD THEREOF 有权
公开(公告)号：US20230083500A1
公开(公告)日：2023-03-16
申请号：US17711807
申请日：2022-04-01
申请人： SK hynix Inc.
发明人： Woo Sick CHOI
IPC分类号： G06F1/3234 , G11C5/14 , G06F1/3225
摘要： A storage device can decrease a leakage current. The storage device includes: a plurality of power switch cells for controlling power supplied to a memory device and a memory controller for controlling the memory device; a power management circuit for providing the plurality of power switch cells with a power voltage corresponding to the power; and a power management circuit controller for controlling the power management circuit to determine a magnitude of the power voltage according to whether the plurality of power switch cells supply the power to the memory device and the memory controller.

2. 发明授权

US11561603B2 Memory device low power mode 有权
公开(公告)号：US11561603B2
公开(公告)日：2023-01-24
申请号：US16719904
申请日：2019-12-18
申请人： Micron Technology, Inc.
发明人： Michael Dieter Richter , Thomas Hein , Wolfgang Anton Spirkl , Martin Brox , Peter Mayer
IPC分类号： G06F1/3234 , G11C5/14 , G06F1/3225
摘要： Methods, systems, and devices for memory device operation are described. A memory device may operate in different modes in response to various conditions and user constraints. Such modes may include a power-saving or low power mode. While in the low power mode, the memory device may refrain from operations, such as self-refresh operations, on one or more of the memory array(s) included in the memory device. The memory device may deactivate external interface components and components that may generate operating voltages for the memory array(s), while the memory device may continue to power circuits that store operating information for the memory device. The memory device may employ similar techniques in other operating modes to accommodate or react to different conditions or user constraints.

3. 发明申请

US20220413583A1 PRECISE POWER CYCLE MANAGEMENT IN DATA STORAGE DEVICES 有权
公开(公告)号：US20220413583A1
公开(公告)日：2022-12-29
申请号：US17682060
申请日：2022-02-28
申请人： Western Digital Technologies, Inc.
发明人： Yoseph Hassan , Dmitry Vaysman , Julian Vlaiko , Shay Benisty
IPC分类号： G06F1/3225 , G06F3/06
摘要： Methods and apparatus for precise power cycle management in data storage devices are provided. One such apparatus is a data storage device that includes a non-volatile memory (NVM) and a processor coupled to the NVM. In such case, the processor is configured to determine a first peak power for a first power phase, operate the DSD at a first DSD power consumption that is less than the first peak power for the first power phase, determine a second peak power for a second power phase based on a residual power equal to a difference between a preselected average power threshold and the first DSD power consumption, and operate the DSD at a second DSD power consumption that is less than the second peak power for the second power phase.

4. 发明申请

US20220397953A1 DYNAMIC POWER CONTROL 有权
公开(公告)号：US20220397953A1
公开(公告)日：2022-12-15
申请号：US17736886
申请日：2022-05-04
申请人： Micron Technology, Inc.
发明人： Junjun Wang , Yanming Liu , Deping He , Hua Tan
IPC分类号： G06F1/3225 , G06F1/3296 , G06F3/06
摘要： Methods, systems, and devices for dynamic power control are described. In some examples, a memory device may be configured to adjust a first duration for transitioning power modes. For example, the memory device may be configured to operate in a first power mode, a second power mode, and a third power mode. When operating in a second power mode, the memory device may be configured to increase or decrease the first duration for transitioning to a third power mode based on a second duration between received commands. If no commands are received during the first duration, the memory device may transition from the second power mode to the third power mode.

5. 发明申请

US20220365690A1 Node Interconnection Apparatus, Resource Control Node, and Server System 有权
公开(公告)号：US20220365690A1
公开(公告)日：2022-11-17
申请号：US17876861
申请日：2022-07-29
申请人： Huawei Technologies Co., Ltd.
发明人： Baifeng Yu , Zhou Yu , Jiongjiong Gu
IPC分类号： G06F3/06 , G06F9/4401 , H04L67/1097 , G06F1/3221 , G06F1/3225 , G06F1/3234 , G06F1/3287 , H04L47/70 , G06F1/3203
摘要： A node interconnection apparatus includes a computing node, a resource control node, and a device interconnection interface connecting the computing node and the resource control node. Each of the computing node and the resource control node includes a processing unit and a storage unit, and the resource control node further includes a resource interface for connecting with a network storage device. The resource control node manages a storage resource of the network storage device, and when the computing node needs to start up, the resource control node obtains operating system startup information from the network storage device and provides the operating system startup information to the computing node. The computing node can start up without the need for storing startup information locally.

6. 发明授权

US11442525B2 Power management 有权
公开(公告)号：US11442525B2
公开(公告)日：2022-09-13
申请号：US16548910
申请日：2019-08-23
申请人： MICRON TECHNOLOGY, INC.
发明人： Xiaojiang Guo
IPC分类号： G06F1/00 , G06F1/324 , G06F1/3225 , G06F1/3234 , G11C5/14 , G11C8/18 , G06F1/3203
摘要： Methods of operating a die might include determining an expected peak current magnitude of the die for a period of time, and outputting the expected peak current magnitude from the die prior to completion of the period of time. Apparatus might be configured to perform similar methods.

7. 发明申请

US20220253123A1 WIDE RANGE POWER MECHANISM FOR OVER-SPEED MEMORY DESIGN 有权
公开(公告)号：US20220253123A1
公开(公告)日：2022-08-11
申请号：US17731967
申请日：2022-04-28
申请人： DELL PRODUCTS L.P.
发明人： Chunge-Wei Wang , Chihchung Lin , Tse-An- Chu , Shih-Wei Yang , Yi Ling Tsai
IPC分类号： G06F1/3225 , G06F9/4401 , G06F1/3228
摘要： A system for controlling an information handling system is disclosed that includes a central processing unit, a memory device, a power supply and a memory speed controller configured to determine one or more system parameters of the central processing unit, the memory device and the power supply, to store a boot setting as a function of the one or more system parameters and to cause a system reboot after storing the boot setting.

8. 发明申请

US20220229483A1 SYSTEM AND METHOD FOR CLOSED-LOOP MEMORY POWER CAPPING 有权
公开(公告)号：US20220229483A1
公开(公告)日：2022-07-21
申请号：US17153583
申请日：2021-01-20
申请人： DELL PRODUCTS, LP
发明人： Hasnain Shabbir , Carlos Henry
IPC分类号： G06F1/3225 , G06F1/20 , G06F11/30
摘要： An information handling system includes a management controller configured to determine whether to initiate control of power consumption of a memory subsystem of the information handling system. A closed-loop memory thermal controller may receive temperature values to determine a temperature setpoint for the memory subsystem, and calculate an error value that is a difference between the temperature setpoint and a temperature measurement. if the error value is within a temperature margin, then the thermal controller may determine a proportional-integral power signal based on the temperature margin and the temperature measurement; and determine a proportional-integral gain based on a maximum rate of change of the temperature measurement between polling events of the temperature measurement and a polling rate of the temperature measurement. The thermal controller may also determine a modified proportional-integral power signal based on the proportional-integral gain, wherein the modified proportional-integral power signal is used to determine a power adjustment value of the memory subsystem; and in response to an initiation from the management controller to control the power consumption of the memory subsystem, control the power consumption of the memory subsystem based on the power adjustment value.

9. 发明申请

US20220199192A1 PEAK POWER MANAGEMENT SELF-CHECK 有权
公开(公告)号：US20220199192A1
公开(公告)日：2022-06-23
申请号：US17249400
申请日：2021-03-01
申请人： Micron Technology, Inc.
发明人： Jeremy Binfet , Liang Yu
IPC分类号： G11C29/50 , G06F1/3225
摘要： A memory device includes a first memory die of a plurality of memory dies, the first memory die comprising a first memory array and a first power management component, wherein the first power management component is configured to send a first test value to one or more other power management components on one or more other memory dies of the plurality of memory dies during a first power management cycle of a first power management token loop. The memory device further includes a second memory die of the plurality of memory dies, the second memory die comprising a second memory array and a second power management component, wherein the second power management component is configured to receive the first test value from the first power management component during the first power management cycle of the first power management token loop and send a second test value to the one or more other power management components on the one or more other memory dies of the plurality of memory dies during a second power management cycle of a second power management token loop. At least one of the first power management component or the second power management component is configured to compare the first test value and the second test value to a set of expected values to determine whether signal connections between the first power management component and the second power management component are functional.

10. 发明申请

US20220129058A1 ARCHITECTURE-BASED POWER MANAGEMENT FOR A MEMORY DEVICE 有权
公开(公告)号：US20220129058A1
公开(公告)日：2022-04-28
申请号：US17573194
申请日：2022-01-11
申请人： Micron Technology, Inc.
发明人： Christophe Vincent Antoine Laurent , Andrea Martinelli , Graziano Mirichigni
IPC分类号： G06F1/3225 , G06F1/3234 , G06F9/4401 , G06F1/3287
摘要： Methods, systems, and devices for architecture-based power management for a memory device are described. Aspects include operating a first memory bank within a memory device in a first mode and a second memory bank within the memory device in a second mode. The memory device may receive a power down command for the first memory bank while operating the first memory bank in the first mode and the second memory bank in the second mode and switch the first memory bank from the first mode to a first low power mode while maintaining the second memory bank in the second mode. The first low power mode corresponds to less power consumption by the first memory bank than the first mode. In some cases, switching the first memory bank from the first mode to the first low power mode includes deactivating circuitry dedicated to the first memory bank.

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