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1. 发明授权

US11630936B2 Robust optimal design method for photovoltaic cells 有权
公开(公告)号：US11630936B2
公开(公告)日：2023-04-18
申请号：US17369105
申请日：2021-07-07
申请人： Northwestern Polytechnical University
发明人： Feng Zhang , Mingying Wu , Xu Zhang , Dongyue Wang , Xiayu Xu , Lei Cheng
IPC分类号： G06F30/373 , G06F30/398 , G06F30/20 , G06F17/11 , G06F17/15 , G06F17/17 , H02S50/00 , H02J7/00 , H01M6/00 , G06F119/02
摘要： This invention relates to a robust optimal design method for photovoltaic cells. Firstly, the deterministic optimal model is established, which is solved by Monte Carlo method to obtain the maximum output power value of optimization objective and its corresponding design variable value, and then the design variable value obtained from deterministic optimization is deemed as the initial point of the mean value of the robust optimal design variable. Later, the robust optimal model is solved by Monte Carlo method in order to obtain the mean value of design variable, and then appropriate materials and manufacturing techniques are selected for corresponding photovoltaic components according to the design variable obtained, so as to achieve the robust optimal design of photovoltaic cells. In fact, this invention improves the output stability and reliability of photovoltaic cells.

2. 发明授权

US11604916B2 Method, system, and electronic device for detecting open/short circuit of PCB design layout 有权
公开(公告)号：US11604916B2
公开(公告)日：2023-03-14
申请号：US17296230
申请日：2019-04-15
申请人： VAYO (SHANGHAI) TECHNOLOGY CO., LTD.
发明人： Shengjie Qian , Fengshou Liu
IPC分类号： G06F30/398 , G06F30/392 , G06F30/3953 , G06F115/12 , G06F119/02
摘要： A method for detecting an open/short circuit on a PCB design layout includes: reading PCB data of a to-be-checked PCB design layout, to output an image of each PCB layer included in the PCB design layout; performing a first connectivity analysis on the image of each PCB layer to classify pad patterns connected with each other in the same layer into a corresponding child network group; performing a second connectivity analysis to classify child network groups in which pad patterns connected by the same electroplated hole, into a corresponding parent network group; reading IPC netlist data of the PCB design layout, to obtain a netlist network group in which each pad pattern is; and determining whether a netlist network relationship of the pad patterns is consistent with a network relationship obtained after the second connectivity analysis in order to determine whether there is an open/short circuit.

3. 发明授权

US11507719B1 Accelerating formal property verification across design versions using sequential equivalence checking 有权
公开(公告)号：US11507719B1
公开(公告)日：2022-11-22
申请号：US17170843
申请日：2021-02-08
申请人： Synopsys, Inc.
发明人： Sudipta Kundu , Mitesh Jain
IPC分类号： G06F30/3323 , G06F30/323 , G06F119/02 , G06F111/04
摘要： A system and method for providing formal property verification across circuit design versions is described. In one embodiment, the system receives a first version and a second version of a circuit design. The received first version has a first set of constraints, a first set of next-state functions representing the first version of the circuit design, and a first property that has been verified as true for the first version of the circuit design. The received second version has a second set of constraints, a second set of next-state functions representing the second version of the circuit design, and a second property for the second version of the circuit design. The described embodiments further construct a composite circuit design based on the first set of constraints, the first set of next-state functions, and the first property and further based on the second set of constraints, the second set of next-state functions, and the second property. A third property is constructed for the composite circuit design in which the first property implies the second property. Some described embodiments output a proof or a counterexample for the second circuit design, based on the proof of the third property for the composite circuit design, since a user of the system and method is trying to verify the second circuit design, not the composite circuit design.

4. 发明授权

US11499945B2 Digital twin model inversion for testing 有权
公开(公告)号：US11499945B2
公开(公告)日：2022-11-15
申请号：US17585343
申请日：2022-01-26
申请人： Vibrant Corporation
发明人： Leanne Jauriqui , Thomas Kohler , Alexander J. Mayes , Julieanne Heffernan , Richard Livings , Eric Biedermann
IPC分类号： G01N29/44 , G01N29/04 , G01N29/52 , G06F30/20 , G06F30/13 , G06F30/17 , G06F30/23 , G06F119/18 , G06F119/02
摘要： Creation and use of a digital twin instance (DTI) for a physical instance of the part. The DTI may be created by a model inversion process such that model parameters are iterated until a convergence criterion related to a physical resonance inspection result and a digital resonance inspection result is satisfied. The DTI may then be used in relation to part evaluation including through simulated use of the part. The physical instance of the part may be evaluated by way of the DTI or the DTI may be used to generate maintenance schedules specific to the physical instance of the part.

5. 发明授权

US11371965B2 Digital twin model inversion for testing 有权
公开(公告)号：US11371965B2
公开(公告)日：2022-06-28
申请号：US17291746
申请日：2020-07-09
申请人： VIBRANT CORPORATION
发明人： Leanne Jauriqui , Thomas Köhler , Alexander J. Mayes , Julieanne Heffernan , Richard Livings , Eric Biedermann
IPC分类号： G01N29/00 , G06F30/20 , G06F30/13 , G06F30/17 , G01N29/44 , G01N29/04 , G01N29/52 , G06F119/18 , G06F119/02
摘要： Creation and use of a digital twin instance (DTI) for a physical instance of the part. The DTI may be created by a model inversion process such that model parameters are iterated until a convergence criterion related to a physical resonance inspection result and a digital resonance inspection result is satisfied. The DTI may then be used in relation to part evaluation including through simulated use of the part. The physical instance of the part may be evaluated by way of the DTI or the DTI may be used to generate maintenance schedules specific to the physical instance of the part.

6. 发明授权

US11250198B2 Method to perform hardware safety analysis without fault simulation 有权
公开(公告)号：US11250198B2
公开(公告)日：2022-02-15
申请号：US17011204
申请日：2020-09-03
申请人： OneSpin Solutions GmbH
发明人： Jörg Grosse
IPC分类号： G06F30/398 , G06F119/02
摘要： A safety analysis method is based on a safety-specific design structural analysis and cone of influence (COI) that does not require fault simulation. The method for performing a safety analysis of an integrated circuit based on a safety-specific design structural analysis and cone of influence comprises generating with a processor a computed set of basic design elements by intersecting two transitive cones of influence, wherein a first cone of influence is a transitive fanin cone of influence starting from a TO element and a second cone of influence is a transitive fanout cone of influence starting from a FROM element.

7. 发明授权

US11216606B1 Method and system for functional safety verification using fault relation rules 有权
公开(公告)号：US11216606B1
公开(公告)日：2022-01-04
申请号：US16942801
申请日：2020-07-30
申请人： Cadence Design Systems, Inc.
发明人： Ophir Turbovich , Muhammad Zoabi , Yuval Shpak
IPC分类号： G06F30/3308 , G06F119/02 , G06F117/04
摘要： A computer implemented method for functional safety verification includes simulating SA0 and/or SA1 faults at a Q output port of each sequential element in a first representation of an electronic design, to determine whether any of the simulated faults is detectable by a safety mechanism, determining, based on one or more fault relation rules and based on a second gate-level representation of the electronic design, whether any of the faults is also detectable by the safety mechanism if occurred at one or more input ports of the respective sequential element or one or more input ports of a clockgate of the respective sequential element, and identifying a remainder of input ports and input ports of a clockgate of each of the sequential elements at which the faults are not determined to be detectable by the safety mechanism based on the one or a plurality of fault relation rules.

8. 发明授权

US11073556B2 Low pin count reversible scan architecture 有权
公开(公告)号：US11073556B2
公开(公告)日：2021-07-27
申请号：US16856094
申请日：2020-04-23
申请人： Mentor Graphics Corporation
发明人： Wu-Tung Cheng , Yu Huang
IPC分类号： G01R31/3177 , G06F30/333 , G01R31/317 , G06F119/12 , G06F119/02
摘要： A circuit comprises a plurality of scan chains configured to perform scan shifting in two opposite directions and a register configured to store a first signal. The first signal determines whether the plurality of scan chains operate in a first mode or a second mode. The plurality of scan chains operating in the first mode is configured to perform, based on a second signal, either scan shifting in a first direction in the two opposite directions or scan capturing during a test; the plurality of scan chains operating in the second mode is configured to perform, based on the second signal, scan shifting in the first direction or a second direction in the two opposite directions.

9. 发明授权

US10754631B2 Tenant upgrade analytics 有权
公开(公告)号：US10754631B2
公开(公告)日：2020-08-25
申请号：US15941714
申请日：2018-03-30
申请人： Microsoft Technology Licensing, LLC
发明人： John D. Skovron , James C. O'Brien , Ramasubramanian Shastri , Claudiu G. Diaconu , Shashidhar Rajashekara , David W. Brodsky , Sandipan Ganguly , Oana Silvia I. Nica
IPC分类号： G06F8/60 , G06F8/65 , G06F11/34 , G06F11/07 , H04L12/24 , H04L12/26 , G06F119/02
摘要： Methods and systems for determining an upgrade readiness metric of a tenant in a cloud environment. One method includes receiving, with an electronic processor, device telemetry data for a plurality of devices associated with a first plurality of tenants in the cloud environment and receiving, with the electronic processor, software telemetry data for a second plurality of tenants in the cloud environment. The method also includes determining, with the electronic processor, the upgrade readiness metric for the tenant based on the device telemetry data and the software telemetry data and displaying the upgrade readiness metric within a user interface.

10. 发明授权

US11565474B2 System and method for build error detection in an additive manufacturing environment 有权
公开(公告)号：US11565474B2
公开(公告)日：2023-01-31
申请号：US16757107
申请日：2018-11-07
申请人： MATERIALISE N.V.
发明人： Christian Rossmann
IPC分类号： B33Y50/02 , B29C64/393 , B33Y10/00 , B29C64/153 , G06F30/23 , G06F119/02 , G06F113/10
摘要： A system and method for detecting, based on a simulation of a build of an object using additive manufacturing, if the build of the object would be flawed or would fail during actual additive manufacturing of the object is provided.

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