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1. 发明授权

US11640357B2 Methods and apparatus to facilitate read-modify-write support in a victim cache 有权
公开(公告)号：US11640357B2
公开(公告)日：2023-05-02
申请号：US16882231
申请日：2020-05-22
申请人： Texas Instruments Incorporated
发明人： Naveen Bhoria , Timothy David Anderson , Pete Michael Hippleheuser
IPC分类号： G06F12/08 , G06F12/00 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to facilitate read-modify-write support in a victim cache. An example apparatus includes a first storage coupled to a controller, a second storage coupled to the controller and parallel coupled to the first storage, and a storage queue coupled to the first storage, the second storage, and to the controller, the storage queue to obtain a memory operation from the controller indicating an address and a first set of data, obtain a second set of data associated with the address from at least one of the first storage and the second storage, merge the first set of data and the second set of data to produce a third set of data, and provide the third set of data for writing to at least one of the first storage and the second storage.

2. 发明授权

US11636040B2 Methods and apparatus for inflight data forwarding and invalidation of pending writes in store queue 有权
公开(公告)号：US11636040B2
公开(公告)日：2023-04-25
申请号：US16882252
申请日：2020-05-22
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Naveen Bhoria , Timothy David Anderson , Pete Michael Hippleheuser
IPC分类号： G06F12/00 , G06F13/00 , G06F12/0888 , G06F12/0891 , G06F9/54 , G06F12/02 , G06F12/0811 , G06F12/128 , G06F12/0817 , G06F12/0804 , G06F9/30 , G11C7/10 , G11C29/42 , G11C29/44 , G06F11/10 , G06F12/0855 , G06F12/12 , G06F12/0806 , G06F12/0815 , G06F12/0853 , G06F13/16 , G06F12/121 , G06F12/0884 , G06F12/0897 , G06F12/0895 , G06F12/0864 , G11C7/22 , G11C5/06 , G06F15/80 , G06F12/0802
摘要： Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

3. 发明申请

US20230061668A1 Cache Memory Addressing 有权
公开(公告)号：US20230061668A1
公开(公告)日：2023-03-02
申请号：US17823480
申请日：2022-08-30
申请人： Micron Technology, Inc.
发明人： Joseph Thomas Pawlowski , Elliott Clifford Cooper-Balis , David Andrew Roberts
IPC分类号： G06F12/084 , G06F12/0853 , G06F12/02 , G06F9/30 , G06F13/16 , G06F12/0864
摘要： Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

4. 发明申请

US20220309004A1 WRITE MERGING ON STORES WITH DIFFERENT PRIVILEGE LEVELS 有权
公开(公告)号：US20220309004A1
公开(公告)日：2022-09-29
申请号：US17842257
申请日：2022-06-16
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Naveen BHORIA , Timothy David ANDERSON , Pete HIPPLEHEUSER
IPC分类号： G06F12/0888 , G11C7/10 , G06F12/0817 , G06F12/0895 , G06F12/0815 , G06F12/02 , G11C29/42 , G06F12/121 , G11C5/06 , G06F11/10 , G06F13/16 , G06F9/30 , G06F9/54 , G06F12/0806 , G06F12/0853 , G06F12/0855 , G06F12/0864 , G06F12/0891 , G06F12/128 , G06F12/0802 , G06F12/0804 , G06F12/0897 , G06F12/12 , G06F15/80 , G11C7/22 , G11C29/44 , G06F12/0811 , G06F12/0884
摘要： A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

5. 发明申请

US20220156180A1 SECURITY CHECK SYSTEMS AND METHODS FOR MEMORY ALLOCATIONS 有权
公开(公告)号：US20220156180A1
公开(公告)日：2022-05-19
申请号：US17539933
申请日：2021-12-01
申请人： Intel Corporation
发明人： David M. Durham , Michael LeMay
IPC分类号： G06F12/02 , G06F12/0853 , G06F11/10 , G06F9/50 , G06F21/60 , G06F12/0871
摘要： A memory controller is to store a unique tag at the mid-point address within each of allocated memory portions. In addition to the tag data, additional metadata may be stored at the mid-point address of the memory allocation. For each memory access operation, an encoded pointer contains information indicative of a size of the memory allocation as well as its own tag data. The processor circuitry compares the tag data included in the encoded pointer with the tag data stored in the memory allocation. If the tag data included in the encoded pointer matches the tag data stored in the memory allocation, the memory operation proceeds. If the tag data included in the encoded pointer fails to match the tag data stored in the memory allocation, an error or exception is generated.

6. 发明申请

US20220066942A1 MULTI-WAY CACHE MEMORY ACCESS 有权
公开(公告)号：US20220066942A1
公开(公告)日：2022-03-03
申请号：US17499834
申请日：2021-10-12
申请人： SHENZHEN GOODIX TECHNOLOGY CO., LTD.
发明人： Bassam S. Kamand , Waleed Younis , Ramon Zuniga , Jagadish Rongali
IPC分类号： G06F12/0895 , G06F12/084 , G06F13/16 , G06F9/30 , G06F12/0853
摘要： A cache memory is disclosed. The cache memory includes an instruction memory portion having a plurality of instruction memory locations configured to store instruction data encoding a plurality of CPU instructions. The cache memory also includes a tag memory portion having a plurality of tag memory locations configured to store tag data encoding a plurality of RAM memory address ranges the CPU instructions are stored in. The instruction memory portion includes a single memory circuit having an instruction memory array and a plurality of instruction peripheral circuits communicatively connected with the instruction memory array. The tag memory portion includes a plurality of tag memory circuits, where each of the tag memory circuits includes a tag memory array, and a plurality of tag peripheral circuits communicatively connected with the tag memory array.

7. 发明申请

US20210318958A1 Cache Memory Addressing 有权
公开(公告)号：US20210318958A1
公开(公告)日：2021-10-14
申请号：US16846266
申请日：2020-04-10
申请人： Micron Technology, Inc.
发明人： Joseph Thomas Pawlowski , Elliott Clifford Cooper-Balis , David Andrew Roberts
IPC分类号： G06F12/084 , G06F12/0853 , G06F12/02 , G06F9/30 , G06F13/16
摘要： Described apparatuses and methods order memory address portions advantageously for cache-memory addressing. An address bus can have a smaller width than a memory address. The multiple bits of the memory address can be separated into most-significant bits (MSB) and least-significant bits (LSB) portions. The LSB portion is provided to a cache first. The cache can process the LSB portion before the MSB portion is received. The cache can use index bits of the LSB portion to index into an array of memory cells and identify multiple corresponding tags. The cache can also check the corresponding tags against lower tag bits of the LSB portion. A partial match may be labeled as a predicted hit, and a partial miss may be labeled as an actual miss, which can initiate a data fetch. With the remaining tag bits from the MSB portion, the cache can confirm or refute the predicted hit.

8. 发明授权

US11061817B2 Memory node with cache for emulated shared memory computers 有权
公开(公告)号：US11061817B2
公开(公告)日：2021-07-13
申请号：US16066355
申请日：2016-12-22
申请人： Teknologian tutkimuskeskus VTT Oy
发明人： Martti Forsell
IPC分类号： G06F12/084 , G06F12/121 , G06F12/0842 , G06F12/0853 , G06F12/0846
摘要： Data memory node (400) for ESM (Emulated Share Memory) architectures (100, 200), comprising a data memory module (402) containing data memory for storing input data therein and retrieving stored data therefrom responsive to predetermined control signals, a multi-port cache (404) for the data memory, said cache being provided with at least one read port (404A, 404B) and at least one write port (404C, 404D, 404E), said cache (404) being configured to hold recently and/or frequently used data stored in the data memory (402), and an active memory unit (406) at least functionally connected to a plurality of processors via an interconnection network (108), said active memory unit (406) being configured to operate the cache (404) upon receiving a multioperation reference (410) incorporating a memory reference to the data memory of the data memory module from a number of processors of said plurality, wherein responsive to the receipt of the multioperation reference the active memory unit (406) is configured to process the multioperation reference according to the type of the multioperation indicated in the reference, utilizing cached data in accordance with the memory reference and data provided in the multioperation reference. A method to be performed by the memory node is also presented.

9. 发明授权

US10929295B2 Accelerating replication of page tables for multi-socket machines 有权
公开(公告)号：US10929295B2
公开(公告)日：2021-02-23
申请号：US16255432
申请日：2019-01-23
申请人： VMware, Inc.
发明人： Jayneel Gandhi , Pratap Subrahmanyam , Irina Calciu , Aasheesh Kolli
IPC分类号： G06F12/00 , G06F12/0853 , G06F12/1045 , G06F12/0804 , G06F12/0817 , G06F12/1009
摘要： Described herein is a method for tracking changes made by an application. Embodiments include determining, by a processor, a write-back of a cache line from a hardware unit associated with a socket of a plurality of sockets to a page table entry of a page table in a memory location associated with the processor. Embodiments include adding, by the processor, the cache line to a list of dirty cache lines. Embodiments include, for each respective cache line in the list of dirty cache lines, identifying, by the processor, a memory location associated with a respective socket of the plurality of sockets corresponding to the respective cache line and updating, by the processor, an entry of a page table replica at the memory location based on the respective cache line.

10. 发明申请

US20200371909A1 VALIDITY OF DATA SETS STORED IN MEMORY 审中-公开
公开(公告)号：US20200371909A1
公开(公告)日：2020-11-26
申请号：US16755815
申请日：2018-01-29
申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
发明人： JEFFREY KEVIN JEANSONNE , ROSILET RETNAMONI BRADUKE , DAVID PLAQUIN , JOSHUA SERRATELLI SCHIFFMAN
IPC分类号： G06F12/02 , G06F12/0891 , G06F12/0831 , G06F12/0853
摘要： An apparatus includes a solid-state a solid-state non-volatile computer memory; and a controller coupled to the memory. The controller to: generate a data set including a tag that indicates that the data set is valid; write the data set into a block of the memory, wherein the block includes multiple addressable locations set to a common first binary value before the write; generate a subsequent data set including a tag that indicates that the subsequent data set is valid; update the tag of the written data set to indicate that the written data set is invalid, wherein the update includes setting an addressable location corresponding to the tag to second binary value different from the first binary value; write the subsequent data set to addressable locations in the block of memory other than the addressable locations of the invalid data set.

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