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1. 发明授权

US06742012B2 Apparatus and method for performing multiplication operations 有权
标题翻译：用于执行乘法运算的装置和方法
公开(公告)号：US06742012B2
公开(公告)日：2004-05-25
申请号：US09748152
申请日：2000-12-27
申请人： Alexander Edward Nancekievill
发明人： Alexander Edward Nancekievill
IPC分类号： G06F752
CPC分类号： G06F7/5324
摘要： The present invention provides an apparatus and method for processing data using a multiplying circuit for performing a multiplication of a W/2 bit data value by a W bit data value. An instruction decoder is provided which is responsive to a multiply instruction to control the multiplying circuit to generate a multiplication result for the computation M×N, where M and N are W bit data words. The multiplying circuit is arranged to execute a first operation in the which the data word N is multiplied by the most significant W/2 bits of the data word M to generate a first intermediate result having 3W/2 bits, and to then execute a second operation in which the data word N is multiplied by the least significant W/2 bits of the data word M to generate a second intermediate result having 3W/2 bits. The first intermediate result is shifted by W/2 with respect to the second intermediate result and added to the second intermediate result to generate the multiplication result. By performing the two parts of the multiplication in reverse order to the conventional approach, it has been found that the complexity of the circuitry can be reduced, and a reduction in power consumption can be achieved.
摘要翻译：本发明提供一种使用乘法电路处理数据的装置和方法，用于执行W / 2位数据值与W位数据值的乘法。提供了一种指令解码器，其响应于乘法指令来控制乘法电路以产生用于计算MxN的乘法结果，其中M和N是W位数据字。乘法电路被配置为执行数据字N与数据字M的最高有效W / 2位相乘的第一操作，以产生具有3W / 2位的第一中间结果，然后执行第二操作数据字N与数据字M的最低有效W / 2位相乘以产生具有3W / 2位的第二中间结果的操作。第一中间结果相对于第二中间结果移位W / 2，并且相加于第二中间结果以产生乘法结果。通过以与常规方法相反的顺序执行乘法的两个部分，已经发现可以减少电路的复杂性，并且可以实现功率消耗的降低。

2. 发明授权

US06711603B1 Fractional, arithmetic unit, fractional arithmetic method, set-up engine for handling graphic images and computer-readable medium 失效
$Fractional, arithmetic unit, fractional arithmetic method, set-up engine for handling graphic images and computer-readable medium$
标题翻译：分数，算术单位，分数运算法，用于处理图形图像的设置引擎和计算机可读介质
公开(公告)号：US06711603B1
公开(公告)日：2004-03-23
申请号：US09583574
申请日：2000-05-31
申请人： Yasuharu Takenaka
发明人： Yasuharu Takenaka
IPC分类号： G06F752
CPC分类号： G06F7/535 , G06F2207/5356
摘要： A fractional arithmetic unit for performing fractional arithmetic operations of different numerators and a common denominator with different precisions as required, the fractional arithmetic unit, including a reciprocal number arithmetic logic unit; and a multiply arithmetic circuit configured to multiply a numerator and a reciprocal number of the denominator as obtained by the reciprocal number arithmetic logic unit. A precision of a calculation performed by the reciprocal number arithmetic logic unit is changed in accordance with a precision as required for each of the fractional arithmetic operations. The multiply arithmetic circuit outputs a result of multiplication as a result of the fractional arithmetic operation, and the results of the fractional arithmetic operations are output with different precisions.
摘要翻译：分数运算单元，用于根据需要执行不同分数的分数运算和具有不同精度的公分母;分数运算单元，包括倒数算术逻辑单元; 以及乘法运算电路，被配置为乘以由所述倒数算术逻辑单元获得的分母和所述分母的倒数。由往复数算术逻辑单元执行的计算精度根据每个分数算术运算所需的精度而改变。乘法运算电路作为分数算术运算的结果输出乘法运算结果，分数运算的结果以不同的精度输出。

3. 再颁专利

USRE38387E1 Multiplier circuit for multiplication operation between binary and twos complement numbers 有权
标题翻译：乘法电路，用于二进制和二进制补码之间的乘法运算
公开(公告)号：USRE38387E1
公开(公告)日：2004-01-13
申请号：US09932284
申请日：2001-08-17
申请人： Raffaele Costa , Anna Faldarini , Laura Formenti
发明人： Raffaele Costa , Anna Faldarini , Laura Formenti
IPC分类号： G06F752
CPC分类号： G06F7/5318 , G06F2207/3812
摘要： A multiplier circuit which multiplies together both natural and two's complement binary numbers, which it receives in the form of electric signals having predetermined logic values, that are applied to input terminals of logic gating circuits. The logic gating circuits provide partial products of the bits of the two binary numbers, and a combinatorial network provides the final sum of the partial products. The partial products that include at least one of the more significant bits of either of the operands are performed by logic gating circuits which can be enabled to complement the partial product. The multiplier circuit further includes additional logic gating circuits which supply the combinatorial network with additive constants with predetermined logic values.

4. 发明授权

US06622154B1 Alternate booth partial product generation for a hardware multiplier 有权
标题翻译：用于硬件乘数的替代展位部分产品生成
公开(公告)号：US06622154B1
公开(公告)日：2003-09-16
申请号：US09467939
申请日：1999-12-21
申请人： Naoki Hayashi , Vijayanand Angarai
发明人： Naoki Hayashi , Vijayanand Angarai
IPC分类号： G06F752
CPC分类号： G06F7/5338
摘要： In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware multipliers is through the use of the Booth algorithm. The alternate Booth partial product generation for hardware multipliers of the present invention is directed to a method and apparatus for eliminating the encoding of the bits of the multiplier prior to entering the partial product generating cell of the present invention which may result in less hardware and increased speed.
摘要翻译：在硬件乘法器中，部分产品的产生是本领域已知的用于有效生产最终产品的过程中的必要步骤。通过使用布斯算法，提高硬件乘法器速度的一种方法。本发明的用于硬件乘法器的替代Booth部分乘积生成涉及一种用于在进入本发明的部分乘积生成单元之前消除乘数的比特的编码的方法和装置，这可能导致较少的硬件和增加速度。

5. 发明授权

US06604120B1 Multiplier power saving design 失效
标题翻译：乘法器节能设计
公开(公告)号：US06604120B1
公开(公告)日：2003-08-05
申请号：US08923133
申请日：1997-09-04
申请人： Edwin De Angel
发明人： Edwin De Angel
IPC分类号： G06F752
CPC分类号： G06F7/53 , G06F7/503 , G06F7/5332
摘要： A digital parallel multiplier has encoders for each segmented bit pair of the multiplier input data which select one of 4 coefficients, based on the sum of the bit pair, that are then applied to the multiplicand input data. The addition of the rows of the scaled multiplicand input data is performed with adders with two data inputs (plus carryin). These adders are cascaded such that normally invalid data ripples through the adder before the final result is achieved. By controlling the time power is applied to the adders most of the intermediate states are eliminated.
摘要翻译：数字并行乘法器具有用于乘法器输入数据的每个分段比特对的编码器，其基于比特对的和选择4个系数中的一个，然后将其应用于被乘数输入数据。通过具有两个数据输入（加进位）的加法器来执行经缩放的被乘数输入数据的行的添加。这些加法器是级联的，使得在达到最终结果之前通常通过无效数据通过加法器波纹。通过控制时间功率被施加到加法器，大多数中间状态被消除。

6. 发明授权

US06567834B1 Implementation of multipliers in programmable arrays 失效
标题翻译：实现可编程阵列中的乘法器
公开(公告)号：US06567834B1
公开(公告)日：2003-05-20
申请号：US09555624
申请日：2000-06-01
申请人： Alan David Marshall , Anthony Stansfield , Jean Vuillemin
发明人： Alan David Marshall , Anthony Stansfield , Jean Vuillemin
IPC分类号： G06F752
CPC分类号： G06F7/527 , G06F7/53 , G06F7/5338 , G06F9/30014 , G06F9/30036 , G06F9/3017 , G06F15/7867
摘要： Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided a method of multiplying a first number by a second number by use of an array of processing devices, each of said processing devices having a plurality of data inputs, a plurality of data outputs, and an instruction input for control of the function of the processing device, wherein said processing devices and an input for the first number and an input for the second number are interconnected by a freely configurable interconnect, and wherein each processing device calculates a partial product for multiplication of one or more bits of the first number with one or more bits of the second number, and for each processing device: the value received at the instruction input is determined by one or more bits of the first number; data inputs are provided by m bits of the second number, and, if appropriate, a carry input to add a carry from a less significant partial product and/or a summation input to sum all the partial products of the same significance; data outputs are provided as a summation output containing the least significant m bits of the partial product and a carry output containing any more significant bits of the partial product.
摘要翻译：在包含小型处理器设备的阵列或其他聚合的FPGA或类似设备中实现乘法器是一个重大困难，导致由于消耗的硅面积而导致的成本增加。因此，提供了一种通过使用处理装置阵列将第一数乘以第二数的方法，每个所述处理装置具有多个数据输入，多个数据输出和用于控制的指令输入其中所述处理装置和用于第一数量的输入和第二数量的输入通过可自由配置的互连互连，并且其中每个处理装置计算用于乘以所述第一数量的一个或多个比特的部分乘积第一号码，具有第二号码的一位或多位，并且对于每个处理设备：在指令输入处接收的值由第一号码的一位或多位确定; 数据输入由第二数量的m位提供，并且如果适当的话，提供进位输入以从较不重要的部分积和/或求和输入中添加进位以求具有相同重要性的所有部分乘积; 数据输出被提供为包含部分乘积的最低有效m位的求和输出和包含部分乘积的任何更高有效位的进位输出。

7. 发明授权

US06546409B1 Digital processing 失效
标题翻译：数字处理
公开(公告)号：US06546409B1
公开(公告)日：2003-04-08
申请号：US09328519
申请日：1999-06-09
申请人： Kar Lik Wong
发明人： Kar Lik Wong
IPC分类号： G06F752
CPC分类号： G06F7/535
摘要： A digital processor and method for performing mathematical division in which performance degradation is mitigated by avoiding left shift and append (14) on the output of an ALU using pre-shift and append (18, 22) of the feedback from the quotient and remainder storage element (R, Q).
摘要翻译：一种用于执行数学分割的数字处理器和方法，其中通过避免左移移位并且使用预先移位和附加（18,22）来自商和余数存储器的反馈来附加（14）ALU的输出来减轻性能下降元素（R，Q）。

8. 发明授权

US06490608B1 Fast parallel multiplier implemented with improved tree reduction schemes 有权
标题翻译：使用改进的树缩减方案实现快速并行乘法器
公开(公告)号：US06490608B1
公开(公告)日：2002-12-03
申请号：US09458542
申请日：1999-12-09
申请人： Jay Zhu
发明人： Jay Zhu
IPC分类号： G06F752
CPC分类号： G06F7/5318
摘要： Parallel multipliers and techniques for reducing Wallace-trees in parallel multipliers to achieve fewer reduction stages. The parallel multipliers of the present invention, in one embodiment, require one fewer stage of reduction than conventional multipliers proposed by Wallace and Dadda. Accordingly, fewer adder components are required. The speed of the parallel multipliers of the present invention is also improved due to the fewer number of reduction stages. In another embodiment, the method of the present invention is applicable to signed multiplication and includes a step of performing trial reduction on an input matrix that has a maximum number of nodes per column K. The trial reduction step is performed with a reduction target of &dgr;L-2 nodes where &dgr;L-1
摘要翻译：并行乘法器和并行乘法器技术，用于减少并行乘法器中的华莱士树，以实现更少的减少阶段。在一个实施例中，本发明的并行乘法器需要比由Wallace和Dadda提出的常规乘法器少一个阶段的还原。因此，需要较少的加法器部件。本发明的并行乘法器的速度也由于减少级数的减少而得到改善。在另一个实施例中，本发明的方法可应用于带符号乘法，并且包括在具有每列K最大数量的节点的输入矩阵上执行试用减少的步骤。使用减法目标为deltaL -2节点，其中δL-1

9. 发明授权

US06470371B1 Parallel multiplier 失效
标题翻译：平行乘法器
公开(公告)号：US06470371B1
公开(公告)日：2002-10-22
申请号：US08976596
申请日：1997-11-24
申请人： Soung Hwi Park
发明人： Soung Hwi Park
IPC分类号： G06F752
CPC分类号： G06F7/5318
摘要： An improved parallel multiplier capable of operating an addition operation by connecting a plurality of dividers sequentially, thus providing more simple circuit and reducing operating time thereof, which includes NXM AND-gates each for ANDing each multiplier bit ranging from a least significant bit to a most significant bit with each multiplicand bit in case of multiplying “N” multiplicand bits and “M” multiplier bits and for performing a partial multiplication and for outputting a least significant bit as a result of the multiplication; and a plurality of input-bits dividers, having 2-, 3-, and 4-input-bits dividers, for receiving an output bit of a corresponding location among a rearranged output bit and a quotient bit outputted from a proceeding input bit in case that the output bits of the AND-gates is shifted to the left by a bit in accordance with a conventional binary multiplication method and for outputting a quotient bit and a remaining bit corresponding to each bit of a multiplication result.
摘要翻译：一种改进的并行乘法器，其能够通过连续地连接多个分频器来进行加法运算，从而提供更简单的电路并减少其运行时间，其中包括NXM与门，每个用于将每个乘法器位从最低有效位到最大在乘以“N”个被乘数位和“M”个乘法器位的情况下用于执行部分乘法并作为乘法的结果输出最低有效位的每个被乘数位的有效位; 以及具有2-，3-和4-输入比特分频器的多个输入比特分频器，用于接收重排输出比特中相应位置的输出比特和从进位输入比特输出的商比特根据常规的二进制相乘方法，与门的输出位向左移位一位，并且用于输出对应于乘法结果的每个位的商位和剩余位。

10. 发明授权

US06463453B1 Low power pipelined multiply/accumulator with modified booth's recoder 失效
标题翻译：低功率流水线乘法/蓄能器，带改装摊位
公开(公告)号：US06463453B1
公开(公告)日：2002-10-08
申请号：US09006054
申请日：1998-01-12
申请人： Keith Duy Dang
发明人： Keith Duy Dang
IPC分类号： G06F752
CPC分类号： G06F7/5443 , G06F7/5338
摘要： A low power high speed multiply/accumulator (100) utilizes a modified Booth's recoder (120) to identify situations to power down the partial product array (130). The modified Booth's recoder (120) is responsive to a NOP signal (116) and a add/subtract signal (118) that result from instruction decode. The partial product array (130) can be partially or fully shut-down to conserve power in response to the recoder (120) detecting certain operands and NOP instructions. It also allows implementation a multiply-and-subtract instruction. The output of the partial product array (130) is registered in a high order product register (142) and a low order product register (144). The low order product register (144) accumulates partial products for multiply-and-accumulate and multiply-and-subtract instructions. The carry bit of the low order product register (144) is added (146) to the high order product register (142) to generate the high order result (152), while the low order result (154) are derived from the low order product register (144).
摘要翻译：低功率高速乘法/累加器（100）利用经修改的布斯的记录器（120）来识别使部分乘积阵列（130）断电的情况。经修改的布斯的记录器（120）响应于由指令解码产生的NOP信号（116）和加法/减法信号（118）。响应于识别器（120）检测某些操作数和NOP指令，部分产品阵列（130）可被部分或全部关闭以节省功率。它还允许实现乘法和减法指令。部分积数组（130）的输出被登记在高阶积积寄存器（142）和低阶积积寄存器（144）中。低阶积积寄存器（144）积累用于乘法和累加和乘法和减法指令的部分乘积。将低阶乘积寄存器（144）的进位位加到高阶乘积寄存器（142）以产生高阶结果（152），而低阶结果（154）从低阶导出产品注册（144）。

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