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1. 发明授权

US11631459B2 Dual compare ternary content addressable memory 有权
公开(公告)号：US11631459B2
公开(公告)日：2023-04-18
申请号：US17282767
申请日：2018-10-30
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： John Alan Wickeraad
IPC分类号： G11C15/04 , G11C11/413 , G11C11/417 , G11C11/00 , G11C15/00 , G11C7/00 , G11C15/02 , G11C11/4093 , G11C11/411 , G11C11/16 , G11C11/412 , G11C11/408 , G11C11/4097
摘要： A ternary content addressable memory (TCAM) semiconductor device includes a first and second data storage portions each connected to a bit line. The first data storage portion is connected to a first word line, and to a first and third group of in series transistors. The second data storage portion is connected to a second word line, and to a second and fourth group of in series transistors. The first group and second group of in series transistors are each connected to a first match line. The first group is connected to a first search line bar, and the second group is connected to a first search line. A third and fourth group of in series transistors are each connected to a second match line. The third group is connected to a second search line, and the fourth group is connected to a second search line bar.

2. 发明申请

US20230098852A1 VARIABLE VOLTAGE BIT LINE PRECHARGE 有权
公开(公告)号：US20230098852A1
公开(公告)日：2023-03-30
申请号：US18061320
申请日：2022-12-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Atul Katoch , Adrian Earle
IPC分类号： G11C11/4094 , G11C11/419 , G11C11/4096 , G11C11/411 , G11C11/4074
摘要： A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.

3. 发明授权

US11521673B2 Variable voltage bit line precharge 有权
公开(公告)号：US11521673B2
公开(公告)日：2022-12-06
申请号：US17175790
申请日：2021-02-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Atul Katoch , Adrian Earle
IPC分类号： G11C7/00 , G11C11/4094 , G11C11/419 , G11C11/4096 , G11C11/411 , G11C11/4074
摘要： A memory device includes an array of memory cells, a bit line connected to the memory cells, and a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level. A bit line precharge circuit has an input terminal configured to receive the power supply voltage at the first voltage level, and the bit line precharge circuit is configured to precharge the bit lines to a second voltage level lower than the first voltage level.

4. 发明授权

US10283185B2 Write assist thyristor-based SRAM circuits and methods of operation 有权
公开(公告)号：US10283185B2
公开(公告)日：2019-05-07
申请号：US14740209
申请日：2015-06-15
申请人： Kilopass Technology, Inc.
发明人： Harry Luan , Bruce L. Bateman , Valery Axelrad , Charlie Cheng , Christophe J. Chevallier
IPC分类号： G11C11/39 , G11C11/34 , G11C11/418 , G11C11/419 , G11C11/411 , G11C11/416 , H01L27/11 , H01L21/8249 , H01L27/06 , H01L27/102 , H01L27/082 , G11C5/14
摘要： A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.

5. 发明申请

US20180068708A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180068708A1
公开(公告)日：2018-03-08
申请号：US15695061
申请日：2017-09-05
申请人： Renesas Electronics Corporation
发明人： Koji NII
IPC分类号： G11C11/408 , G11C11/4097 , G11C11/412 , G11C11/4093 , G11C11/16 , G11C11/411 , G11C7/24 , G11C7/10
CPC分类号： G11C11/4087 , G11C7/1048 , G11C7/24 , G11C11/1697 , G11C11/4085 , G11C11/4093 , G11C11/4097 , G11C11/411 , G11C11/4125 , G11C15/04
摘要： A semiconductor device includes: a first cell; a second cell; a first match line and a second match line; a first search line pair, first data being transmitted through the first search line pair; a second search line pair, second data being transmitted through the second search line pair; a first logical operation cell connected to the first search line pair and the first match line, and configured to drive the first match line based on a result of comparison between information held by the first and second cells and the first data; and a second logical operation cell connected to the second search line pair and the second match line, and configured to drive the second match line based on a result of comparison between information held by the first and second cells and the second data.

6. 发明授权

US09466346B2 Semiconductor device and information processing device 有权
标题翻译：半导体装置及信息处理装置
公开(公告)号：US09466346B2
公开(公告)日：2016-10-11
申请号：US14639589
申请日：2015-03-05
申请人： Hitachi Ltd.
发明人： Masanao Yamaoka , Chihiro Yoshimura
IPC分类号： G06F12/02 , G11C7/22 , G11C11/406 , G11C11/411 , G06N7/00 , G06N99/00
CPC分类号： G11C7/222 , G06F12/0246 , G06F2212/7201 , G06N7/005 , G06N99/002 , G11C11/40615 , G11C11/411
摘要： A semiconductor device has a plurality of units, each of which includes a first memory cell that stores a value indicating a state of one node of an interaction model, a second memory cell that stores an interaction coefficient indicating an interaction from a node connected to the one node, and a third memory cell that stores a bias coefficient of the one node. Furthermore, the semiconductor device has a computing circuit that determines a value indicating a next state of the one node based on a value indicating a state of the connected node, the interaction coefficient and the bias coefficient. Also, each of the second memory cell and the third memory cell in the plurality of units includes multi-valued memory cells.
摘要翻译：半导体器件具有多个单元，每个单元包括存储指示交互模型的一个节点的状态的值的第一存储器单元，存储指示来自连接到所述交互模块的节点的交互的交互系数的第二存储器单元一个节点和存储该一个节点的偏置系数的第三存储器单元。此外，半导体器件具有基于表示连接节点的状态的值，相互作用系数和偏置系数来确定表示一个节点的下一状态的值的计算电路。此外，多个单元中的第二存储单元和第三存储单元中的每一个包括多值存储单元。

7. 发明授权

US09269422B2 Two transistor ternary random access memory 有权
标题翻译：两个晶体管三元随机存取存储器
公开(公告)号：US09269422B2
公开(公告)日：2016-02-23
申请号：US14500055
申请日：2014-09-29
申请人： Simon Peter Tsaoussis
发明人： Simon Peter Tsaoussis
IPC分类号： G11C11/34 , G11C11/411 , G11C7/12
CPC分类号： G11C11/40 , G11C7/12 , G11C11/39 , G11C11/411 , G11C2207/12
摘要： A two transistor ternary random access memory (TTTRAM) circuit includes an voltage/current input, an input/output switch, a first transistor, a first pull up resistor, a second transistor, and a second pull up resistor. The first transistor has a first emitter, a first collector connected to the input/output switch, and a first base. The first pull up resistor is connected to the first emitter and the voltage/current input. The second transistor has a second emitter connected to ground, a second collector, and a second base connected to the input/output switch. The second pull up resistor is connected to the first base, the second collector, and the voltage/current input.
摘要翻译：双晶体管三元随机存取存储器（TTTRAM）电路包括电压/电流输入，输入/输出开关，第一晶体管，第一上拉电阻，第二晶体管和第二上拉电阻。第一晶体管具有第一发射极，连接到输入/输出开关的第一集电极和第一基极。第一个上拉电阻连接到第一个发射极和电压/电流输入。第二晶体管具有连接到地的第二发射极，第二集电极和连接到输入/输出开关的第二基极。第二个上拉电阻连接到第一个基极，第二个集电极和电压/电流输入。

8. 发明申请

US20070274125A1 Enhanced Programming Performance in a Nonvolatile Memory Device Having a Bipolar Programmable Storage Element 审中-公开
标题翻译：具有双极可编程存储元件的非易失性存储器件中的增强的编程性能
公开(公告)号：US20070274125A1
公开(公告)日：2007-11-29
申请号：US11839239
申请日：2007-08-15
申请人： Johannes Bednorz , John DeBrosse , Chung Lam , Gerhard Meijer , Jonathan Sun
发明人： Johannes Bednorz , John DeBrosse , Chung Lam , Gerhard Meijer , Jonathan Sun
IPC分类号： G11C11/411
CPC分类号： G11C11/16 , G11C11/5685 , G11C13/0007 , G11C2213/31 , G11C2213/79
摘要： A nonvolatile memory cell includes a bipolar programmable storage element operative to store a logic state of the memory cell, and a metal-oxide-semiconductor device including first and second source/drains and a gate. A first terminal of the bipolar programmable storage element is adapted for connection to a first bit line. The first source/drain is connected to a second terminal of the bipolar programmable storage element, the second source/drain is adapted for connection to a second bit line, and the gate is adapted for connection to a word line.
摘要翻译：非易失性存储单元包括可操作地存储存储单元的逻辑状态的双极可编程存储元件和包括第一和第二源极/漏极和栅极的金属氧化物半导体器件。双极可编程存储元件的第一端子适于连接到第一位线。第一源极/漏极连接到双极可编程存储元件的第二端子，第二源极/漏极适于连接到第二位线，并且栅极适于连接到字线。

9. 发明授权

US5959334A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5959334A
公开(公告)日：1999-09-28
申请号：US850743
申请日：1997-05-02
申请人： Yukio Maki , Hiroki Honda
发明人： Yukio Maki , Hiroki Honda
IPC分类号： G11C11/411 , H01L21/8244 , H01L27/10 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L27/11 , Y10S257/903
摘要： A bipolar transistor is formed by forming a base region continuing from a source/drain region of an MOS transistor, as a link base region, and forming an emitter region at a bit line contact hole by impurity implantation. Alternatively, the bipolar transistor is formed by forming an intrinsic base region and an emitter region at a bit line contact hole by impurity implantation. The intrinsic base region is made deeper than the source/drain region. Further, the impurity of the intrinsic base region is made different from that of the link base region.
摘要翻译：通过形成从MOS晶体管的源极/漏极区域连续的基极区域作为连接基极区域，并且通过杂质注入在位线接触孔处形成发射极区域来形成双极晶体管。或者，双极晶体管通过通过杂质注入在位线接触孔处形成本征基极区域和发射极区域而形成。本征基极区域比源极/漏极区域更深。此外，本征基区的杂质与链接基区的杂质不同。

10. 发明授权

US5864511A Semiconductor memory device using cross-coupled load and precharge circuit for bit line pairs 失效
标题翻译：半导体存储器件使用交叉耦合负载和预充电电路进行位线对
公开(公告)号：US5864511A
公开(公告)日：1999-01-26
申请号：US991781
申请日：1997-12-16
申请人： Hirotoshi Sato
发明人： Hirotoshi Sato
IPC分类号： G11C11/41 , G11C7/12 , G11C11/411 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C7/12
摘要： Bit lines (BL, /BL) are equally held low by a low-level precharge circuit (212) and an equalizing circuit (218) at time (t1) prior to a read operation. A read signal (/READ) and an equalization signal (EQ) go low at time (t2) when the read operation starts to provide "H" to word lines (WLU, WLL). If storage nodes (N1, N2) store "H" and "L" respectively, a bipolar transistor (BP2) is activated when the bit line (/BL) reaches a potential (+Vbe). Then, the potential of the bit line (/BL) does not rise to a power supply potential (VCC) but is held at the potential (+Vbe). Current flows to the bit line (/BL) through a reading load circuit (211) transiently (for a time period between times t2 and t3), but no current flows to the bit line (/BL) in a steady state (for a time period between times t3 and t4).
摘要翻译：在读取操作之前的时间（t1），位线（BL，/ BL）被低电平预充电电路（212）和均衡电路（218）同等地保持为低电平。当读取操作开始向字线（WLU，WLL）提供“H”时，读取信号（/ READ）和均衡信号（EQ）在时间（t2）变低。如果存储节点（N1，N2）分别存储“H”和“L”，则当位线（/ BL）达到电位（+ Vbe）时，双极晶体管（BP2）被激活。然后，位线（/ BL）的电位不会上升到电源电位（VCC），而是保持在电位（+ Vbe）。电流通过读取负载电路（211）瞬时流过位线（/ BL）（在时间t2和t3之间的时间段），但是没有电流稳定地流向位线（/ BL）（对于时间t3和时间t4之间）。

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