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1. 发明授权

US08848417B2 Integrated circuit with a self-programmed identification key 有权
标题翻译：具有自编程识别键的集成电路
公开(公告)号：US08848417B2
公开(公告)日：2014-09-30
申请号：US13607578
申请日：2012-09-07
申请人： Emmanuel Petitprez
发明人： Emmanuel Petitprez
IPC分类号： G11C17/04 , H01L23/00 , H01L23/544 , H01L23/525 , H01L49/02 , H01L23/522
CPC分类号： H01L23/544 , H01L23/5223 , H01L23/5252 , H01L23/576 , H01L28/40 , H01L2223/5444 , H01L2223/5448 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： A structure for storing a native binary code in an integrated circuit, including an array of planar MIM capacitors above an insulating layer formed above a copper metallization network, wherein at least one metallization portion is present under each MIM capacitor. The size of the portion(s) is selected so that from 25 to 75% of the MIM capacitors have a breakdown voltage smaller by at least 10% than that of the other MIM capacitors.
摘要翻译：一种用于在集成电路中存储本机二进制码的结构，包括在铜金属化网络上形成的绝缘层之上的平面MIM电容器阵列，其中在每个MIM电容器下方存在至少一个金属化部分。选择部分的尺寸，使得25％至75％的MIM电容器的击穿电压比其他MIM电容器的击穿电压小至少10％。

2. 发明申请

US20130058150A1 OTP MEMORY 有权
公开(公告)号：US20130058150A1
公开(公告)日：2013-03-07
申请号：US13584899
申请日：2012-08-14
申请人： Kenichi HIDAKA , Yoshitaka KUBOTA
发明人： Kenichi HIDAKA , Yoshitaka KUBOTA
IPC分类号： G11C17/16 , G11C17/04
CPC分类号： H01L27/11206 , G11C17/16 , G11C17/18 , H01L28/40
摘要： The present invention provides an OTP memory having higher confidentiality. A memory cell has a memory transistor forming a current path between first and second nodes, a selection transistor forming a current path between third and fourth nodes, the third node being coupled to the gate of the memory transistor via a line, and a capacitor coupled to the first node. By applying high voltage which does not break but deteriorates a gate oxide film and increases gate leak current to a memory transistor, data is written. Data can be read by the presence/absence of leak of charges accumulated in the capacitor. Since the position of deterioration in the gate oxide film cannot be discriminated by a physical analysis, confidentiality is high.

3. 发明申请

US20130051111A1 ANTI-FUSE CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：防冻电路和集成电路，包括它们
公开(公告)号：US20130051111A1
公开(公告)日：2013-02-28
申请号：US13300212
申请日：2011-11-18
申请人： Keon YOO
发明人： Keon YOO
IPC分类号： G11C17/04
CPC分类号： G11C17/18
摘要： An anti-fuse circuit and an integrated circuit (IC) including the same are disclosed, which are applied to a technology for use in all kinds of semiconductor devices or system ICs, each of which includes an anti-fuse circuit using the breakdown phenomenon of a gate oxide, so as to prevent the occurrence of an anti-breakdown phenomenon. The anti-fuse circuit includes an anti-fuse, a breakdown of which occurs by a program voltage, configured to be electrically short-circuited, a read controller configured to be controlled by a read voltage received through the anti-fuse so as to output a short-circuiting status of the anti-fuse, and a switching unit configured to form a path that prevents a current flowing through the anti-fuse from being applied to the read controller during a program operation and prevents a current from flowing in the anti-fuse during a read operation.
摘要翻译：公开了一种抗熔丝电路及其集成电路（IC），其应用于各种半导体器件或系统IC中使用的技术，其中每个包括使用击穿现象的反熔丝电路栅极氧化物，以防止发生抗分解现象。反熔丝电路包括反熔丝，其被构造为电短路的编程电压发生击穿，配置为由通过反熔丝接收的读取电压控制的读取控制器，以便输出反熔丝的短路状态，以及开关单元，其被配置为形成在程序操作期间防止流过反熔丝的电流被施加到读取控制器的路径，并防止电流在反向熔断中流动 - 在读操作期间进行。

4. 发明申请

US20100061137A1 One-time programmable read only memory 失效
标题翻译：一次性可编程只读存储器
公开(公告)号：US20100061137A1
公开(公告)日：2010-03-11
申请号：US12205867
申请日：2008-09-06
申请人： Juhan Kim
发明人： Juhan Kim
IPC分类号： G11C17/04 , G11C7/00
CPC分类号： G11C7/18 , G11C7/06 , G11C17/16 , G11C17/18 , G11C2207/002
摘要： For realizing high speed one time programmable memory, bit line is multi-divided for reducing capacitance, so that the bit line is quickly charged when reading and multi-stage sense amps are used for connecting divided bit line, wherein the multi-stage sense amps are composed of a first dynamic circuit serving as a local sense amp for reading the memory cell, a second dynamic circuit serving as a segment sense amp for reading the local sense amp, and a tri-state inverter serving as an amplify circuit of a global sense amp for reading the segment sense amp. When reading data, a voltage difference in the bit line is converted to a time difference for differentiating high data (programmed) and low data (unprogrammed) by the multi-stage sense amps. And buffered data path is connected to the global sense amp for realizing fast data transfer. Additionally, alternative circuits and memory cell structures are described.
摘要翻译：为了实现高速一次可编程存储器，位线被多重分割以减小电容，使得当读取时位线快速充电，并且多级感测放大器用于连接分开的位线，其中多级感测放大器由作为用于读取存储单元的本地读出放大器的第一动态电路，用作读取本地读出放大器的段读出放大器的第二动态电路和用作全局的放大电路的三态反相器用于读取段感测放大器的感测放大器。当读取数据时，通过多级感测放大器将位线中的电压差转换为用于区分高数据（编程）和低数据（未编程）的时间差。并且缓冲数据路径连接到全局感测放大器，以实现快速的数据传输。另外，描述了替代电路和存储单元结构。

5. 发明授权

UST977006I4 Read only memory with optimized dimension for improved performance and chip area utilization 失效
标题翻译：只读存储器具有优化的尺寸，以提高性能和芯片面积利用率
公开(公告)号：UST977006I4
公开(公告)日：1978-12-05
申请号：US899615
申请日：1978-04-24
申请人： Peruvemba S. Balasubramanian , Edwin C. Grazier , John D. Henke , Robert P. Latham , Martin J. Myers
发明人： Peruvemba S. Balasubramanian , Edwin C. Grazier , John D. Henke , Robert P. Latham , Martin J. Myers
IPC分类号： G11C17/04 , G11C17/12 , H01L27/10 , H01L27/112
CPC分类号： H01L27/10 , G11C17/12 , H01L27/112
摘要： a read only memory on a semiconductor substrate having metal word lines and diffused bit lines with optimized dimensions for a selected performance and storage capacity with the metal lines being along an X dimension and the diffused lines being orthogonally related to the metal lines along a Y dimension. The X dimension for the substrate is given by the relation X = 2.sup.N .multidot. WL .multidot. K1 where 2.sup.N is an integer definitive of the number of words on a metal line where N is any integer power greater than zero; WL is word length which equals the number of storage devices per word selected for a word and K1 is a constant definitive of the average spacing in mils between the storage devices along the first length, and the Y dimension being given by a second relation Y = K2 .multidot. QN where K2 is a constant definitive of the spacing in mils between the adjacent rows of storage devices along the second length and Q is the number of said words. Changing the aspect ratio for an array permits the performance of a read only memory to be changed to a different set of X and Y dimensions.

6. 发明授权

US3827032A Differentially coupled memory arrays 失效
标题翻译：不同的联接存储器阵列
公开(公告)号：US3827032A
公开(公告)日：1974-07-30
申请号：US26400072
申请日：1972-06-19
申请人： INTEGRATED MEMORIES INC
发明人： ABBOTT W , CHEN T
IPC分类号： G11C17/04 , G11C11/24 , G11C17/00
CPC分类号： G11C17/04
摘要： A read-only memory plane has a plurality of storage elements arranged in a matrix of columns and rows. Drive means are associated with the columns of elements for energizing the elements and a plurality of sense lines are associated with the row of elements for determining the information content of the storage elements. A second matrix of storage elements is within the memory plane in tandem with the first matrix of elements. A second set of drive means and sense lines are provided for the read-out of the second array of storage elements. The information read-out is manifest in the presence or absence of signals induced in the sense lines when the storage elements are energized. Pairs of sense lines one in each pair from the first array and the other from the second array, are coupled to respective differential amplifiers for amplifying the induced signals and for rejecting any stray signals including background noise which would be common to the two arrays.
摘要翻译：只读存储器平面具有排列成列和行的矩阵的多个存储元件。驱动装置与用于激励元件的元件列相关联，并且多个感测线与用于确定存储元件的信息内容的元件行相关联。存储元件的第二矩阵在与存储器平面内的第一矩阵的元件之间。第二组驱动装置和感测线被提供用于读出第二存储元件阵列。当存储元件被通电时，在存在或不存在感测线中感应的信号的情况下，显示信息读出。耦合到相应的差分放大器，用于放大感应信号和拒绝任何杂散信号，包括两个阵列共有的背景噪声。

7. 发明授权

US3506969A Balanced capacitor read only storage using a single balance line for the two drive lines and slotted capacitive plates to increase fringing 失效
标题翻译：平衡电容器使用单个平衡线读取两个驱动线和插槽电容板以增加FRINGING
公开(公告)号：US3506969A
公开(公告)日：1970-04-14
申请号：US3506969D
申请日：1967-04-04
申请人： IBM
发明人： ABBAS SHAKIR A
IPC分类号： G11C17/00 , G11C17/04 , G11C5/02
CPC分类号： G11C17/00 , G11C17/04

8. 发明授权

US3461436A Matrix-type,permanent memory device 失效
标题翻译：矩阵型，永久存储器件
公开(公告)号：US3461436A
公开(公告)日：1969-08-12
申请号：US3461436D
申请日：1965-08-06
申请人： TRANSITRON ELECTRONIC CORP
发明人： NAVON DAVID H , BAKALAR DAVID
IPC分类号： G11C17/04 , G11B3/00
CPC分类号： G11C17/04 , Y10T29/435 , Y10T29/49117

9. 发明授权

US3404452A Method of making a memory device component and the like 失效
标题翻译：制造存储器件组件等的方法
公开(公告)号：US3404452A
公开(公告)日：1968-10-08
申请号：US48861165
申请日：1965-09-20
申请人： DAVID H. NAVON , DAVID BAKALAR
发明人： NAVON DAVID H , DAVID BAKALAR
IPC分类号： G11C17/04 , H01G4/06
CPC分类号： H01G4/06 , G11C17/04 , Y10T29/49069

10. 发明授权

US3373409A Information storage unit and memory card therefor 失效
标题翻译：信息存储单元及其存储卡
公开(公告)号：US3373409A
公开(公告)日：1968-03-12
申请号：US44943265
申请日：1965-04-20
申请人： IBM
发明人： LORD PHILIP A
IPC分类号： G11C17/04
CPC分类号： G11C17/04

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