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1. 发明授权

US06826075B2 Random access semiconductor memory with reduced signal overcoupling 失效
标题翻译：随机存取半导体存储器，减少信号超耦合
公开(公告)号：US06826075B2
公开(公告)日：2004-11-30
申请号：US09905853
申请日：2001-07-13
申请人： Dietmar Gogl , Thomas Röhr , Heinz Hönigschmid
发明人： Dietmar Gogl , Thomas Röhr , Heinz Hönigschmid
IPC分类号： G11C506
CPC分类号： G11C11/16 , G11C7/18 , H01L27/222
摘要： A memory matrix has at least one cell array including column lines and row lines. Memory elements are situated at points where the row lines and column lines intersect one another. In each case two adjacent lines are guided such that they cross one another in such a way that the two lines change their spatial configurations in sections along the direction in which they run. Thus an overcoupling of signals between the lines is minimized.
摘要翻译：存储器矩阵具有至少一个包括列线和行线的单元阵列。存储元件位于行线和列线彼此相交的点处。在每种情况下，两个相邻的线被引导使得它们彼此交叉，使得两条线沿着它们运行的方向在其部分中改变它们的空间构造。因此，线路之间的信号过度耦合被最小化。

2. 发明授权

US06819580B2 Semiconductor chip selectively providing a predetermined potential to a dead pin 失效
标题翻译：半导体芯片选择性地为死针提供预定电位
公开(公告)号：US06819580B2
公开(公告)日：2004-11-16
申请号：US10356537
申请日：2003-02-03
申请人： Masayuki Konishi , Takehiko Shimomura
发明人： Masayuki Konishi , Takehiko Shimomura
IPC分类号： G11C506
CPC分类号： G11C5/14 , G11C5/066 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C2207/105
摘要： A semiconductor chip is provided, with which presence of dead pins can be easily noticed and a process for controlling the potential at dead pins can be performed easily. An input/output controller (IOC) for coordinating the input/output of signals through individual pins (PN1 to PN8) includes an input/output buffer (BFa) and the input/output buffer (BFa) includes a switch (SW4a) and a switch (SW4b). A setting memory (STMa) for storing settings for control of the input/output of signals in the input/output buffer (BFa) contains a memory table and the memory table contains an item about the dead pin potential control process so that a power-supply potential (Vdd) or a ground potential (GND) can be applied to the dead pins, i.e. the fourth pin (PN4) and the fifth pin (PN4).
摘要翻译：提供了一种半导体芯片，可以容易地看到死针的存在，并且可以容易地执行用于控制死针的电位的处理。用于通过各个引脚（PN1至PN8）协调信号的输入/输出的输入/输出控制器（IOC）包括输入/输出缓冲器（BFa），输入/输出缓冲器（BFa）包括开关（SW4a）和开关（SW4b）。用于存储用于控制输入/输出缓冲器（BFa）中的信号的输入/输出的设置的设置存储器（STMa）包含存储表，并且存储表包含关于死端电位控制处理的项目，供电电位（Vdd）或接地电位（GND）可以施加到死针，即第四针（PN4）和第五针（PN4）。

3. 发明授权

US06813175B2 Interconnection layout of a semiconductor memory device 有权
标题翻译：半导体存储器件的互连布局
公开(公告)号：US06813175B2
公开(公告)日：2004-11-02
申请号：US10253926
申请日：2002-09-25
申请人： Hyo-Joo Ahn , Byong-Mo Moon , Hyun-Kyoung Kim
发明人： Hyo-Joo Ahn , Byong-Mo Moon , Hyun-Kyoung Kim
IPC分类号： G11C506
CPC分类号： G11C5/063
摘要： An interconnection layout includes alternately arranged data-read lines and data-write lines. The data-write lines are maintained at a ground voltage level when the data-read lines in a transitional state, and the data-read lines are maintained at the ground voltage level when the data-write lines in a transitional state. Therefore, a coupling capacitance is not produced between adjacent data-write lines and adjacent data-read lines.
摘要翻译：互连布局包括交替布置的数据读取线和数据写入线。当数据读取线处于过渡状态时，数据写入线保持在接地电压电平，并且数据读取线保持在接地电压电平。因此，在相邻的数据写入线和相邻的数据读取线之间不产生耦合电容。

4. 发明授权

US06807078B2 Semiconductor input/output circuit arrangement 有权
标题翻译：半导体输入/输出电路布置
公开(公告)号：US06807078B2
公开(公告)日：2004-10-19
申请号：US10229337
申请日：2002-08-26
申请人： William Thies , Nicolas Froidevaux
发明人： William Thies , Nicolas Froidevaux
IPC分类号： G11C506
CPC分类号： H01L27/0207 , H01L23/5286 , H01L24/06 , H01L2224/05554 , H01L2224/06153
摘要： A method produces a semiconductor circuit with an area saving in comparison to conventional circuit layouts. IO cells are arranged with a width multiplied by a factor, but with corresponding reduced height. ESD protection circuitry is included at a reduced rate in comparison to usual arrangements. The space saving is achieved by occupying a semiconductor area that would have been used by ESD circuitry with the IO circuitry. ESD protection is maintained but at different locations.
摘要翻译：与常规电路布局相比，一种方法产生了具有面积节省的半导体电路。 IO单元被布置成宽度乘以因子，但具有相应减小的高度。与常规安排相比，ESD保护电路以降低的速度被包括在内。通过占用由ESD电路与IO电路一起使用的半导体区域来实现节省空间。 ESD保护保持在不同的位置。

5. 发明授权

US06795327B2 Semiconductor storage method and device supporting multi-interface 失效
标题翻译：半导体存储方法和器件支持多接口
公开(公告)号：US06795327B2
公开(公告)日：2004-09-21
申请号：US10261001
申请日：2002-09-30
申请人： Guoshun Deng , Xiaohua Cheng , Feng Xiang
发明人： Guoshun Deng , Xiaohua Cheng , Feng Xiang
IPC分类号： G11C506
CPC分类号： G06F3/0607 , G06F3/0661 , G06F3/0679 , G11C7/1006
摘要： A semiconductor storage method and device supporting multi-interface includes the acts of setting up a semiconductor storage device in which is installed a semiconductor storage medium module, a controller module, and an interface module which supports at least two interfaces of different standards, wherein the interfaces include serial or parallel or wireless communication interfaces; connecting the storage device, through the interfaces of different standards, to at least one data processing system which has the corresponding standard interface; establishing information exchange channel between the storage device and the data processing system based upon the serial or parallel or wireless communication interfaces; the storage device exchanges data with the data processing system through the information exchange channel. The method is to provide convenient mobile storage devices for data processing systems that have different interfaces, and to make data and files exchange easily and conveniently among different data processing systems.
摘要翻译：一种半导体存储方法和支持多接口的装置包括设置半导体存储装置的动作，其中安装有半导体存储介质模块，控制器模块和支持至少两个不同标准接口的接口模块，其中，接口包括串行或并行或无线通信接口; 通过不同标准的接口将存储设备连接到具有相应标准接口的至少一个数据处理系统; 基于串行或并行或无线通信接口在存储设备和数据处理系统之间建立信息交换通道; 存储装置通过信息交换通道与数据处理系统交换数据。该方法是为具有不同接口的数据处理系统提供方便的移动存储设备，并且在不同的数据处理系统之间方便地进行数据和文件的交换。

6. 发明授权

US06771526B2 Method and apparatus for data transfer 有权
标题翻译：用于数据传输的方法和装置
公开(公告)号：US06771526B2
公开(公告)日：2004-08-03
申请号：US10073475
申请日：2002-02-11
申请人： Paul A. LaBerge
发明人： Paul A. LaBerge
IPC分类号： G11C506
CPC分类号： G06F13/4234
摘要： An electronic system includes a memory module configured to operate in multiple modes. The memory module includes at least one connection configured to perform different functions when the memory module is operating in different modes. In one embodiment, the memory operates in a normal mode and an SPD mode. While in SPD mode, the connection performs one or more SPD functions, such as operating as an SMBus interface connection. In normal mode, the connection serves a function associated with normal operation of the module, such as addressing functions.
摘要翻译：电子系统包括被配置为以多种模式操作的存储器模块。存储器模块包括至少一个被配置为当存储器模块以不同模式操作时执行不同功能的连接。在一个实施例中，存储器以正常模式和SPD模式运行。在SPD模式下，连接执行一个或多个SPD功能，例如作为SMBus接口连接操作。在正常模式下，连接起到与模块正常运行相关的功能，如寻址功能。

7. 发明授权

US06765814B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06765814B2
公开(公告)日：2004-07-20
申请号：US10315042
申请日：2002-12-10
申请人： Ryuji Nishihara , Hiroyuki Sadakata
发明人： Ryuji Nishihara , Hiroyuki Sadakata
IPC分类号： G11C506
CPC分类号： G11C5/063 , G11C8/14
摘要： Strap lines are provided in a layer above word lines so that the word lines and the strap lines are connected to each other in strapping regions separately provided at the ends of memory cell array portions in a conventional semiconductor memory device having a problem wherein the area of the memory cell array portions is increased. Each memory cell is formed of a MOS transistor and a MOS capacitor in a layout of a memory cell array portion according to a standard CMOS process. Memory cells of this structure have a sufficiently large pitch between bit lines and, therefore, contacts for connecting word lines to strap lines in an upper layer are provided between the bit lines, as low resistance metal wires, in the same layer as the bit lines. Thereby, it becomes unnecessary to separately provide strapping regions at the ends of memory cell array portions and it becomes unnecessary to increase the intervals between the memory cells by increasing the size of the memory cell in the layout according to the standard CMOS process and, therefore, contacts for strapping word lines can be provided for each memory cell, without increasing the area of memory cell array portions or the chip area, so that the propagation delay of drive signals in word lines can be reduced and high speed memory operation can be implemented.
摘要翻译：带状线设置在字线上方的层中，使得字线和带线彼此连接在具有问题的常规半导体存储器件中的分开设置在存储单元阵列部分的端部处的带状区域中，其中，存储单元阵列部分增加。根据标准CMOS工艺，每个存储单元由存储单元阵列部分的布局中的MOS晶体管和MOS电容器形成。这种结构的存储单元在位线之间具有足够大的间距，因此，用于将字线连接到上层中的带线的触点设置在与位线相同的层中作为低电阻金属线的位线。因此，不需要在存储单元阵列部分的端部分开提供带状区域，并且不需要通过根据标准CMOS工艺增加布局中的存储单元的尺寸来增加存储单元之间的间隔，因此可以为每个存储单元提供用于捆扎字线的触点，而不增加存储单元阵列部分或芯片面积的面积，从而可以减少字线中的驱动信号的传播延迟并且可以实现高速存储器操作。

8. 发明授权

US06762949B2 Dynamic RAM-and semiconductor device 有权
标题翻译：动态RAM和半导体器件
公开(公告)号：US06762949B2
公开(公告)日：2004-07-13
申请号：US10627713
申请日：2003-07-28
申请人： Hiroki Fujisawa , Riichiro Takemura , Koji Arai
发明人： Hiroki Fujisawa , Riichiro Takemura , Koji Arai
IPC分类号： G11C506
CPC分类号： H01L27/0207 , G11C5/025 , G11C5/063 , G11C7/18 , G11C8/08 , G11C11/4097 , H01L27/10882 , H01L27/10885 , H01L27/10897
摘要： A semiconductor memory includes a plurality of memory arrays and a plurality of sense amplifiers arranged alternately with respect to each of the memory arrays. The sense amplifiers are coupled to bit lines of the memory arrays to form an open bit line type semiconductor memory. In conjunction with this structure, two memory arrays at end portions of the semiconductor memory device are both selected together, whereas a memory array in an inner portion of the semiconductor memory device is selected independently.
摘要翻译：半导体存储器包括相对于每个存储器阵列交替布置的多个存储器阵列和多个读出放大器。读出放大器耦合到存储器阵列的位线，以形成开放位线型半导体存储器。结合这种结构，半导体存储器件的端部处的两个存储器阵列都被一起选择，而半导体存储器件的内部部分中的存储器阵列被独立地选择。

9. 发明授权

US06717834B2 Dual bus memory controller 有权
标题翻译：双总线内存控制器
公开(公告)号：US06717834B2
公开(公告)日：2004-04-06
申请号：US10108243
申请日：2002-03-26
申请人： Steven W. Zagorianakos , Donald McManus
发明人： Steven W. Zagorianakos , Donald McManus
IPC分类号： G11C506
CPC分类号： G11C11/4093 , G06F13/1663 , G11C7/10
摘要： A memory controller initiates a first memory access in response to receipt of a first memory access request. The memory controller receives a second memory access request and initiates a second memory access in response to receipt of the second memory request prior to completing the first memory access.
摘要翻译：响应于接收到第一存储器访问请求，存储器控制器启动第一存储器访问。存储器控制器接收第二存储器访问请求，并且在完成第一存储器访问之前响应于接收到第二存储器请求而启动第二存储器访问。

10. 发明授权

US06717833B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06717833B2
公开(公告)日：2004-04-06
申请号：US09750625
申请日：2000-12-12
申请人： Goro Kitsukawa , Yoji Idei , Kanji Oishi , Akira Ide
发明人： Goro Kitsukawa , Yoji Idei , Kanji Oishi , Akira Ide
IPC分类号： G11C506
CPC分类号： G11C7/10
摘要： A 64Mb DRAM includes memory cell array areas 15, sense amplifier areas 16, subword driver areas 17, and cross areas 18. For each horizontal input/output line IOH paraleel to the word line W, throuh holes on the sense amplifiers provide connections between the second metal line hierarchy M2 and the third metal line hierarchy M3. The vertical input/output line IOV parallel to the bit line BL runs through a plurality of memory cell array areas 15 in a direction parallel to the column selection signal line YS and connects to the main amplifier MA outside the memory cell array areas 15. In this input/output line configuration, the greater the number of word lines W that are selected, the greater the number of bits that can be output.
摘要翻译： 64Mb DRAM包括存储单元阵列区域15，读出放大器区域16，子字驱动器区域17和交叉区域18.对于到字线W的每个水平输入/输出线路IOH路由器，传感放大器上的孔洞提供第二金属线层级M2和第三金属线层级M3。与位线BL并联的垂直输入/输出线IOV沿与列选择信号线YS平行的方向延伸穿过多个存储单元阵列区域15，并连接到存储单元阵列区域15外的主放大器MA。该输入/输出线配置，所选择的字线W的数量越大，可以输出的位数越大。

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