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1. 发明授权

US09219056B2 Passive devices for FinFET integrated circuit technologies 有权
标题翻译： FinFET集成电路技术的无源器件
公开(公告)号：US09219056B2
公开(公告)日：2015-12-22
申请号：US13431347
申请日：2012-03-27
申请人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
发明人： William F. Clark, Jr. , Robert J. Gauthier, Jr. , Junjun Li
IPC分类号： H01L27/06 , H01L21/20 , H01L21/33 , H01L27/02 , H01L21/8249 , H01L21/84 , H01L29/06 , H01L27/12
CPC分类号： H01L27/0262 , G06F17/5072 , H01L21/8249 , H01L21/845 , H01L27/0255 , H01L27/06 , H01L27/1211 , H01L29/06
摘要： Device structures, design structures, and fabrication methods for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A portion of a device layer of a semiconductor-on-insulator substrate is patterned to form a device region. A well of a first conductivity type is formed in the epitaxial layer and the device region. A doped region of a second conductivity type is formed in the well and defines a junction with a portion of the well. The epitaxial layer includes an exterior sidewall spaced from an exterior sidewall of the device region. Another portion of the device layer may be patterned to form fins for fin-type field-effect transistors.
摘要翻译：无源器件的器件结构，设计结构和制造方法可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。将绝缘体上半导体衬底的器件层的一部分图案化以形成器件区域。在外延层和器件区域中形成第一导电类型的阱。在阱中形成第二导电类型的掺杂区域并且限定与阱的一部分的结。外延层包括与器件区域的外侧壁间隔开的外侧壁。可以对器件层的另一部分进行构图以形成翅片型场效应晶体管的鳍片。

2. 发明授权

US09034703B2 Self aligned contact with improved robustness 有权
标题翻译：自对准接触，改善了坚固性
公开(公告)号：US09034703B2
公开(公告)日：2015-05-19
申请号：US13613436
申请日：2012-09-13
申请人： Kangguo Cheng , Ali Khakifirooz , Shom Ponoth , Raghavasimhan Sreenivasan
发明人： Kangguo Cheng , Ali Khakifirooz , Shom Ponoth , Raghavasimhan Sreenivasan
IPC分类号： H01L21/33 , H01L21/28 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/66 , H01L29/78
CPC分类号： H01L29/42364 , H01L21/28079 , H01L29/495 , H01L29/511 , H01L29/66545 , H01L29/78 , H01L29/7833
摘要： A method of forming a semiconductor device including providing a functional gate structure on a channel portion of a semiconductor substrate. A gate sidewall spacer is adjacent to the functional gate structure and an interlevel dielectric layer is present adjacent to the gate sidewall spacer. The upper surface of the gate conductor is recessed relative to the interlevel dielectric layer. A multi-layered cap is formed a recessed surface of the gate structure, wherein at least one layer of the multi-layered cap includes a high-k dielectric material and is present on a sidewall of the gate sidewall spacer at an upper surface of the functional gate structure. Via openings are etched through the interlevel dielectric layer selectively to at least the high-k dielectric material of the multi-layered cap, wherein at least the high-k dielectric material protects a sidewall of the gate conductor.
摘要翻译：一种形成半导体器件的方法，包括在半导体衬底的沟道部分上提供功能栅极结构。栅极侧壁间隔物与功能栅极结构相邻，并且层间介质层邻近栅极侧壁间隔物存在。栅极导体的上表面相对于层间电介质层凹陷。多层盖形成了栅极结构的凹陷表面，其中多层盖的至少一层包括高k电介质材料，并且存在于栅侧壁间隔物的侧壁上功能门结构。通过开孔蚀刻穿过层间电介质层至少至多层多层盖的高k电介质材料，其中至少高k绝缘材料保护栅极导体的侧壁。

3. 发明授权

US08895455B2 Method for manufacturing semiconductor device and substrate processing apparatus 有权
标题翻译：半导体装置及基板处理装置的制造方法
公开(公告)号：US08895455B2
公开(公告)日：2014-11-25
申请号：US14074183
申请日：2013-11-07
申请人： Hitachi Kokusai Electric Inc.
发明人： Naonori Akae , Yoshiro Hirose
IPC分类号： H01L21/33 , H01L21/469 , H01L21/285 , H01L21/314 , H01L21/02 , H01L21/316 , H01L21/318 , H01L21/321
CPC分类号： H01L21/022 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02238 , H01L21/02247 , H01L21/02274 , H01L21/0228 , H01L21/02326 , H01L21/3141 , H01L21/3145 , H01L21/31612 , H01L21/3185
摘要： To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.
摘要翻译：在膜中形成具有极低浓度杂质如碳，氢，氮，氯等的绝缘膜。提供了通过将含有特定元素的源气体供给到容纳基板的处理容器中而在基板上形成特定含有元素层的步骤; 通过将含氮气体活化并供给到处理容器中，将含特定元素的层改变成氮化物层; 以及通过激活和供应含氧气体到所述处理容器中来将所述氮化物层改变为氧化物层或氧氮化物层; 将该循环设置为一个循环并执行至少一次或多次。

4. 发明授权

US08658508B2 Method for manufacturing SOI substrate 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US08658508B2
公开(公告)日：2014-02-25
申请号：US13411864
申请日：2012-03-05
申请人： Takeshi Shichi , Junichi Koezuka , Hideto Ohnuma , Shunpei Yamazaki
发明人： Takeshi Shichi , Junichi Koezuka , Hideto Ohnuma , Shunpei Yamazaki
IPC分类号： H01L21/33 , H01L21/8222
CPC分类号： H01L27/1266 , H01L21/76254 , H01L27/1214 , H01L29/66772
摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.
摘要翻译：本发明提供一种制造SOI衬底的方法，即使在非质量分离型离子照射方法为非质子分离型离子照射方法的情况下，通过有利地分离单晶半导体衬底来提高分离后的单晶半导体层的表面的平面性并且在分离之后提高单晶半导体层的表面的平面性以及提高生产量。该方法包括以下步骤：当单晶半导体衬底被冷却以在单晶半导体衬底中形成脆化区域时，通过离子掺杂方法照射具有加速离子的单晶半导体衬底; 将单晶半导体衬底和基底衬底之间插入绝缘层; 并且沿着脆化区域分离单晶半导体衬底，以在基底衬底上形成绝缘层，形成单晶半导体层。

5. 发明申请

US20110303947A1 APPARATUS AND METHOD FOR PROTECTING ELECTRONIC CIRCUITS 有权
标题翻译：用于保护电子电路的装置和方法
公开(公告)号：US20110303947A1
公开(公告)日：2011-12-15
申请号：US12797461
申请日：2010-06-09
申请人： Javier A. Salcedo , David Casey , Graham McCorkell
发明人： Javier A. Salcedo , David Casey , Graham McCorkell
IPC分类号： H01L27/06 , H01L21/33
CPC分类号： H01L27/0259
摘要： Apparatuses and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type.
摘要翻译：公开了用于电子电路保护的装置和方法。在一个实施例中，装置包括具有发射极和集电极区的阱。阱具有第一类型的掺杂，并且发射极和集电极区域具有第二类型的掺杂。发射极区域，阱极和集电极区域分别被配置为用作第一晶体管的发射极，基极和集电极。集电极区域与发射极区域间隔开以限定间隔。第一间隔件和第二间隔件位于发射器和收集器之间的阱附近。导电板定位成邻近阱并且位于第一间隔件和第二间隔件之间，并且与第一间隔件相邻的掺杂，第二间隔件和板基本上由第一类型组成。

6. 发明授权

US08049231B2 Quantum photonic imagers and methods of fabrication thereof 有权
标题翻译：量子光子成像器及其制造方法
公开(公告)号：US08049231B2
公开(公告)日：2011-11-01
申请号：US12728069
申请日：2010-03-19
申请人： Hussein S. El-Ghoroury , Robert G. W. Brown , Dale A. McNeill , Huibert DenBoer , Andrew J. Lanzone
发明人： Hussein S. El-Ghoroury , Robert G. W. Brown , Dale A. McNeill , Huibert DenBoer , Andrew J. Lanzone
IPC分类号： H01L21/33
CPC分类号： H01S5/4043 , B82Y20/00 , G09G3/2018 , G09G3/32 , G09G2300/0842 , G09G2310/0235 , G09G2340/06 , H01S5/02276 , H01S5/105 , H01S5/18 , H01S5/2009 , H01S5/3063 , H01S5/34326 , H01S5/34333 , H01S5/4093 , H04N9/3161
摘要： Emissive quantum photonic imagers comprised of a spatial array of digitally addressable multicolor pixels. Each pixel is a vertical stack of multiple semiconductor laser diodes, each of which can generate laser light of a different color. Within each multicolor pixel, the light generated from the stack of diodes is emitted perpendicular to the plane of the imager device via a plurality of vertical waveguides that are coupled to the optical confinement regions of each of the multiple laser diodes comprising the imager device. Each of the laser diodes comprising a single pixel is individually addressable, enabling each pixel to simultaneously emit any combination of the colors associated with the laser diodes at any required on/off duty cycle for each color. Each individual multicolor pixel can simultaneously emit the required colors and brightness values by controlling the on/off duty cycles of their respective laser diodes.
摘要翻译：发射量子光子成像器由数字可寻址多色像素的空间阵列组成。每个像素是多个半导体激光二极管的垂直堆叠，每个半导体激光二极管可以产生不同颜色的激光。在每个多色像素内，通过耦合到包括成像器装置的多个激光二极管中的每一个的光限制区域的多个垂直波导，从二极管堆产生的光被垂直于成像器装置的平面发射。包括单个像素的每个激光二极管是可单独寻址的，使得每个像素可以在每个颜色的任何所需的开/关占空比下同时发射与激光二极管相关联的颜色的任何组合。每个单色多色像素可以通过控制其各自的激光二极管的开/关占空比同时发出所需的颜色和亮度值。

7. 发明授权

US08003474B2 Electrically programmable fuse and fabrication method 有权
标题翻译：电可编程保险丝和制造方法
公开(公告)号：US08003474B2
公开(公告)日：2011-08-23
申请号：US12192387
申请日：2008-08-15
申请人： Kaushik Chanda , Ronald G. Filippi , Joseph M. Lukaitis , Ping-Chuan Wang
发明人： Kaushik Chanda , Ronald G. Filippi , Joseph M. Lukaitis , Ping-Chuan Wang
IPC分类号： H01L21/33
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse includes an anode, a cathode, and a fuse link conductively connecting the cathode with the anode, which is programmable by applying a programming current. The anode and the fuse link each include a polysilicon layer and a silicide layer formed on the polysilicon layer, and the cathode includes the polysilicon layer and a partial silicide layer formed on a predetermined portion of the polysilicon layer of the cathode located adjacent to a cathode junction where the cathode and the fuse link meet.
摘要翻译：电可编程保险丝包括阳极，阴极和导电地连接阴极与阳极的熔断体，其可通过施加编程电流来编程。阳极和熔丝链路各自包括形成在多晶硅层上的多晶硅层和硅化物层，并且阴极包括多晶硅层和形成在阴极的多晶硅层的预定部分上的部分硅化物层，其位于阴极附近阴极和熔断体连接处的连接处。

8. 发明授权

US07977185B2 Method and apparatus for post silicide spacer removal 有权
标题翻译：后硅化物间隔物去除的方法和装置
公开(公告)号：US07977185B2
公开(公告)日：2011-07-12
申请号：US11164417
申请日：2005-11-22
申请人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
发明人： Brian J. Greene , Chung Woh Lai , Yong Meng Lee , Wenhe Lin , Siddhartha Panda , Kern Rim , Young Way Teh
IPC分类号： H01L21/33
CPC分类号： H01L21/31116 , H01L21/31144 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
摘要翻译：后硅化物间隔物去除的方法（和装置）包括通过使用氧化物层和氮化物层中的至少一种来防止对硅化物间隔物的损害。

9. 发明申请

US20090111228A1 SELF ALIGNED RING ELECTRODES 有权
标题翻译：自对准环电极
公开(公告)号：US20090111228A1
公开(公告)日：2009-04-30
申请号：US11924073
申请日：2007-10-25
申请人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Brandon Yee
发明人： Matthew J. Breitwisch , Eric A. Joseph , Chung H. Lam , Alejandro G. Schrott , Brandon Yee
IPC分类号： H01L21/33
CPC分类号： H01L21/76843 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： The present invention in one embodiment provides a method of manufacturing an electrode that includes providing at least one metal stud positioned in a via extending into a first dielectric layer, wherein an electrically conductive liner is positioned between at least a sidewall of the via and the at least one metal stud; recessing an upper surface of the at least one metal stud below an upper surface of the first dielectric layer to provide at least one recessed metal stud; and forming a second dielectric atop the at least one recessed metal stud, wherein an upper surface of the electrically conductive liner is exposed.
摘要翻译：本发明在一个实施例中提供了一种制造电极的方法，其包括提供定位在延伸到第一介电层中的通孔中的至少一个金属柱，其中导电衬垫定位在通孔的至少侧壁和在最少一个金属螺柱; 将所述至少一个金属螺柱的上表面凹陷在所述第一介电层的上表面下方，以提供至少一个凹入的金属柱; 以及在所述至少一个凹入的金属螺柱的顶部上形成第二电介质，其中所述导电衬垫的上表面被暴露。

10. 发明申请

US20090026491A1 TUNNELING EFFECT TRANSISTOR WITH SELF-ALIGNED GATE 有权
标题翻译：具有自对准门的隧道效应晶体管
公开(公告)号：US20090026491A1
公开(公告)日：2009-01-29
申请号：US11828740
申请日：2007-07-26
申请人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman
发明人： Roger A. Booth, JR. , Kangguo Cheng , Jack A. Mandelman
IPC分类号： H01L29/70 , H01L21/33
CPC分类号： H01L29/7391 , H01L23/485 , H01L29/66356 , Y10S438/926 , Y10S438/979
摘要： In one embodiment, a mandrel and an outer dummy spacer may be employed to form a first conductivity type region. The mandrel is removed to form a recessed region wherein a second conductivity type region is formed. In another embodiment, a mandrel is removed from within shallow trench isolation to form a recessed region, in which an inner dummy spacer is formed. A first conductivity type region and a second conductivity region are formed within the remainder of the recessed region. An anneal is performed so that the first conductivity type region and the second conductivity type region abut each other by diffusion. A gate electrode is formed in self-alignment to the p-n junction between the first and second conductivity regions. The p-n junction controlled by the gate electrode, which may be sublithographic, constitutes an inventive tunneling effect transistor.
摘要翻译：在一个实施例中，可以使用心轴和外部虚拟间隔件来形成第一导电类型区域。去除心轴以形成其中形成第二导电类型区域的凹陷区域。在另一个实施例中，心轴从浅沟槽隔离中移除以形成凹陷区域，其中形成内部虚拟间隔物。第一导电类型区域和第二导电区域形成在凹陷区域的其余部分内。进行退火，使得第一导电类型区域和第二导电类型区域通过扩散彼此邻接。栅电极形成为与第一和第二导电区域之间的p-n结自对准。由栅电极控制的可能是亚光刻的p-n结构成本发明的隧道效应晶体管。

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