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1. 发明授权

US06833588B2 Semiconductor device having a U-shaped gate structure 有权
公开(公告)号：US06833588B2
公开(公告)日：2004-12-21
申请号：US10274867
申请日：2002-10-22
申请人： Bin Yu , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang
发明人： Bin Yu , Shibly S. Ahmed , Judy Xilin An , Srikanteswara Dakshina-Murthy , Zoran Krivokapic , Haihong Wang
IPC分类号： H01L2701
CPC分类号： H01L29/785 , H01L29/41733 , H01L29/42384 , H01L29/66795 , H01L29/66803
摘要： A double-gate semiconductor device includes a substrate, an insulating layer, a fin and a gate. The insulating layer is formed on the substrate and the gate is formed on the insulating layer. The fin has a number of side surfaces, a top surface and a bottom surface. The bottom surface and at least a portion of the side surfaces of the fin are surrounded by the gate. The gate material surrounding the fin has a U-shaped cross-section at a channel region of the semiconductor device.

2. 发明授权

US06825534B2 Semiconductor device on a combination bulk silicon and silicon-on-insulator (SOI) substrate 有权
标题翻译：组合体硅和绝缘体上硅（SOI）衬底上的半导体器件
公开(公告)号：US06825534B2
公开(公告)日：2004-11-30
申请号：US09748256
申请日：2000-12-27
申请人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
发明人： Howard H. Chen , Louis L. Hsu , Li-Kong Wang
IPC分类号： H01L2701
CPC分类号： H01L21/76264 , H01L21/02381 , H01L21/0243 , H01L21/02532 , H01L21/02675 , H01L21/02689 , H01L21/2022 , H01L21/76283 , H01L21/84
摘要： A semiconductor device includes a combination substrate having a bulk silicon region, and a silicon-on-insulator (SOI) region. The SOI region includes a crystallized silicon layer formed by annealing amorphous silicon and having isolation trenches formed therein so as to remove defective regions, and isolation oxides formed in the isolation trenches.
摘要翻译：半导体器件包括具有体硅区域和绝缘体上硅（SOI）区域的组合衬底。 SOI区域包括由非晶硅退火形成的结晶硅层，并且在其中形成有隔离沟槽，以去除不良区域，以及在隔离沟槽中形成隔离氧化物。

3. 发明授权

US06806537B2 Semiconductor device having offset insulation film formed on insulation film, and method of manufacturing the same 有权
标题翻译：具有在绝缘膜上形成的偏移绝缘膜的半导体器件及其制造方法
公开(公告)号：US06806537B2
公开(公告)日：2004-10-19
申请号：US10192657
申请日：2002-07-11
申请人： Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
发明人： Takuji Matsumoto , Hirokazu Sayama , Shigenobu Maeda , Toshiaki Iwamatsu , Kazunobu Ota
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L21/76283 , H01L21/84 , H01L27/12 , H01L27/1203 , H01L29/4238 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/78615 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).
摘要翻译：提供一种半导体器件，其通过降低寄生双极晶体管的增益来实现故障的减小和工作特性变化，及其制造方法。在硅层（3）的上表面上部分地形成氧化硅膜（6）。多晶硅的栅电极（7）部分地形成在氧化硅膜（6）上。栅电极（7）下方的氧化硅膜（6）的一部分用作栅极绝缘膜。在栅极（7）的每个侧表面上形成氮化硅膜（9），其间具有氧化硅膜（8）。氧化硅膜（8）和氮化硅膜（9）形成在氧化硅膜（6）上。氧化硅膜（8）在栅极长度方向上的宽度（W1）大于氧化硅膜（6）的厚度（T1）。

4. 发明授权

US06784492B1 Semiconductor device including a gate-insulated transistor 失效
标题翻译：半导体器件包括栅极绝缘晶体管
公开(公告)号：US06784492B1
公开(公告)日：2004-08-31
申请号：US08250942
申请日：1994-05-31
申请人： Masakazu Morishita
发明人： Masakazu Morishita
IPC分类号： H01L2701
CPC分类号： H01L29/105 , H01L29/1033 , H01L29/78
摘要： A semiconductor device comprises at least a semiconductor layer including source and drain areas of a first conductive type and of a high impurity concentration and a channel area positioned between the source and drain areas, an insulation layer covering at least the channel area, and a gate electrode positioned close to the insulation layer. The channel area at least comprises a first channel area of a low resistance, positioned close to the insulation layer and having a second conductive type opposite to the first conductive type, and a second channel area of a high resistance, having the first conductive type and positioned adjacent to the first channel area.
摘要翻译：半导体器件至少包括半导体层，其包括第一导电类型和高杂质浓度的源极和漏极区域以及位于源极和漏极区域之间的沟道区域，至少覆盖沟道区域的绝缘层和栅极电极靠近绝缘层定位。通道区域至少包括低电阻的第一通道区域，其位于绝缘层附近并且具有与第一导电类型相反的第二导电类型和具有第一导电类型的高电阻的第二沟道区域，以及定位在第一通道区域附近。

5. 发明授权

US06770936B2 Thin film transistors, and liquid crystal display device and electronic apparatus using the same 失效
标题翻译：薄膜晶体管，液晶显示装置及使用其的电子装置
公开(公告)号：US06770936B2
公开(公告)日：2004-08-03
申请号：US09077207
申请日：1998-05-26
申请人： Satoshi Inoue , Ichio Yudasaka
发明人： Satoshi Inoue , Ichio Yudasaka
IPC分类号： H01L2701
CPC分类号： H01L27/124 , G02F1/13454 , H01L23/3672 , H01L29/41725 , H01L29/41733 , H01L29/42384 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： In a TFT including on the surface side of a substrate a channel region opposed to a gate electrode, with a gate insulating film provided therebetween, and a source-drain region connected to the channel region, and a TFT including a source-drain wiring layer electrically connected to the source-drain region, and a gate wiring layer electrically connected to the gate electrode, at least one component part composed of a conductive film or a semiconductor film, among the component parts of each TFT, is provided with a heat-radiating extension extended from the component part itself for enhancing the heat-radiating efficiency from the component part.
摘要翻译：在包括在基板的表面侧的TFT中，与栅电极相对的沟道区域，其间设置有栅极绝缘膜的TFT以及与沟道区域连接的源极 - 漏极区域，以及包括源极 - 漏极布线层电连接到源极 - 漏极区域，以及栅极布线层，电连接到栅极电极，至少一个由导电膜或半导体膜构成的部件，在每个TFT的部件中设置有热 - 从部件本身延伸的辐射延伸部，用于增强部件的散热效率。

6. 发明授权

US06770935B2 Array of transistors with low voltage collector protection 有权
标题翻译：具有低电压采集器保护的晶体管阵列
公开(公告)号：US06770935B2
公开(公告)日：2004-08-03
申请号：US10166965
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , Dale Skelton
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , Dale Skelton
IPC分类号： H01L2701
CPC分类号： H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/1083 , H01L29/7835
摘要： An array (90) of transistors (50) formed in a p-type layer (34), and including a second heavily doped p-type region (56) laterally extending proximate the drain of each transistor to collect minority carriers of the transistors. A deep n-type region (16) is formed in the p-type layer (34) and proximate a n-type buried layer (14) together forming a guardring about the drain regions of the plurality of transistors. The array of transistors may be interconnected in parallel to form a large power FET, whereby the heavily doped second p-type region (56) reduces the minority carrier lifetime proximate the drains of the transistors. The guardring (14, 16) collects the minority carriers (T1) and is isolated from the drains of the transistors. Preferably, the transistors are formed in a P-epi tank that is isolated by the guardring. The P-epi tank is preferably formed upon a buried NBL layer, and the deep n-type region is an N+ well extending to the buried NBL layer. The guardring is preferably grounded when utilized as the low side transistor to collect minority carriers.
摘要翻译：形成在p型层（34）中的晶体管（50）的阵列（90），并且包括在每个晶体管的漏极附近横向延伸以收集晶体管的少数载流子的第二重掺杂p型区域（56）。在p型层（34）中形成深n型区域（16）并邻近n型掩埋层（14），形成围绕多个晶体管的漏极区域的保护。晶体管阵列可以并联连接以形成大功率FET，由此重掺杂的第二p型区域（56）减少了靠近晶体管漏极的少数载流子寿命。防护（14,16）收集少数载流子（T1），并与晶体管的漏极隔离。优选地，晶体管形成在由护罩隔离的P-epi罐中。 P-epi罐优选地形成在掩埋NBL层上，并且深n型区域是延伸到掩埋NBL层的N +阱。当用作低侧晶体管以收集少数载流子时，护罩优选地接地。

7. 发明授权

US06762464B2 N-p butting connections on SOI substrates 有权
公开(公告)号：US06762464B2
公开(公告)日：2004-07-13
申请号：US10245933
申请日：2002-09-17
申请人： Clair Webb , Mark Bohr
发明人： Clair Webb , Mark Bohr
IPC分类号： H01L2701
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： An SOI connection for connecting source/drain regions of one transistor to source/drain regions of another transistor without the use of overlying metal. The regions abut, and a salicide interconnects the regions.

8. 发明授权

US06730964B2 Semiconductor device and method of producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06730964B2
公开(公告)日：2004-05-04
申请号：US10260656
申请日：2002-10-01
申请人： Masatada Horiuchi
发明人： Masatada Horiuchi
IPC分类号： H01L2701
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/105 , H01L27/10873 , H01L27/11 , H01L27/1104 , H01L27/11803 , H01L27/1203
摘要： A semiconductor device has a MOSFET formed on a single crystalline silicon layer in an SOI structure in which the silicon layer is laminated along with an insulator on a handle wafer. To prevent the body floating effect, a recombination center region is formed connecting to the lower surfaces of source and drain regions of the MOSFET. Consequently, the holes generated within the single crystalline silicon layer just beneath a channel of the MOSFET are injected into the recombination center region by way of the single crystalline silicon layer beneath the source diffusion region and eliminated so that the body floating effect is prevented.
摘要翻译：半导体器件具有形成在SOI结构中的单晶硅层上的MOSFET，其中硅层与处理晶片上的绝缘体层叠。为了防止身体浮动效应，形成连接到MOSFET的源极和漏极区域的下表面的复合中心区域。因此，刚好在MOSFET的通道正下方的单晶硅层内产生的空穴通过源极扩散区域下方的单晶硅层被注入到复合中心区域，并被消除，从而防止了浮体效应。

9. 发明授权

US06717213B2 Creation of high mobility channels in thin-body SOI devices 有权
标题翻译：在薄体SOI器件中创建高迁移率通道
公开(公告)号：US06717213B2
公开(公告)日：2004-04-06
申请号：US09895579
申请日：2001-06-29
申请人： Brian S. Doyle , Brian E. Roberds
发明人： Brian S. Doyle , Brian E. Roberds
IPC分类号： H01L2701
CPC分类号： H01L21/76254 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/02664
摘要： A method for fabricating a strained silicon film to a silicon on insulation (SOI) wafer. A layer of oxide is deposited onto a wafer that has a stack structure of a first base substrate, a layer of relaxed film and a second layer of strained film. The SOI wafer has a stack structure of a second base substrate and a layer of oxidized film. The SOI wafer is attached to the wafer and is heated at a first temperature. This causes a silicon dioxide (SiO2) dangling bond to form on the second base substrate of the SOI wafer, transferring the strained film from one wafer to the other.
摘要翻译：一种将应变硅膜制造到绝缘硅（SOI）晶片上的方法。一层氧化物沉积在具有第一基底基底，松弛膜层和第二层应变膜的堆叠结构的晶片上。 SOI晶片具有第二基底基板和氧化膜层的堆叠结构。 SOI晶片连接到晶片并在第一温度下被加热。这导致在SOI晶片的第二基底衬底上形成二氧化硅（SiO 2）悬挂键，将应变膜从一个晶片转移到另一个晶片。

10. 发明授权

US06693326B2 Semiconductor device of SOI structure 失效
标题翻译： SOI结构的半导体器件
公开(公告)号：US06693326B2
公开(公告)日：2004-02-17
申请号：US09822251
申请日：2001-04-02
申请人： Alberto O. Adan
发明人： Alberto O. Adan
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/7841 , H01L29/78612 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device of SOI structure comprises a surface semiconductor layer in a floating state, which is stacked on a buried insulating film so as to construct an SOI substrate, source/drain regions of second conductivity type which are formed in the surface semiconductor layer, a channel region of first conductivity type between the source/drain regions and a gate electrode formed on the channel region through a gate insulating film; wherein the surface semiconductor layer has a potential well of the first conductivity type formed therein at and/or near at least one end of the channel region in a gate width direction thereof.
摘要翻译： SOI结构的半导体器件包括浮置状态的表面半导体层，其被堆叠在埋入绝缘膜上以构成SOI衬底，形成在表面半导体层中的第二导电类型的源/漏区，源极/漏极区域之间的第一导电类型的沟道区域和通过栅极绝缘膜形成在沟道区域上的栅电极; 其中所述表面半导体层在其栅极宽度方向上在沟道区的至少一端处和/或附近形成有第一导电类型的势阱。

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