专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06815738B2 Multiple gate MOSFET structure with strained Si Fin body 有权
公开(公告)号：US06815738B2
公开(公告)日：2004-11-09
申请号：US10377388
申请日：2003-02-28
申请人： Kern Rim
发明人： Kern Rim
IPC分类号： H01L2980
CPC分类号： H01L29/785 , H01L21/845 , H01L29/1054 , H01L29/66795 , H01L29/7842
摘要： A method is disclosed for fabricating multifaceted, tensilely strained Si MOSFET (FinFET) devices. The method comprises the growing by selective epitaxy of a monocrystalline Si strip onto a monocrystalline SiGe layer sidewall surface, where the SiGe layer is bonded to a support platform, typically an insulator on a Si substrate, and where the Si strip also bonds to the support platform. The SiGe sidewall surface has a lattice constant which is larger than the relaxed lattice constant of Si, whereby the Si strip is in a tensilely strained state. Upon removing the SiGe monocrystalline layer the monocrystalline strained Si strip is turned into a multifaceted Si strip on the support platform, suitable for fabricating multifaceted gate FinFETs. Fabrication of processors with such FinFet devices is also disclosed.

2. 发明授权

US06800886B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06800886B2
公开(公告)日：2004-10-05
申请号：US10435471
申请日：2003-05-12
申请人： Yuji Awano
发明人： Yuji Awano
IPC分类号： H01L2980
CPC分类号： H01L23/5226 , B82Y10/00 , H01L23/3677 , H01L23/373 , H01L23/481 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device comprises insulation films 30a-30f formed on a semiconductor substrate 10, and a thermal conductor 42 buried in the insulation films. The thermal conductor is formed on a tube structure of carbon atoms. The thermal conductor is formed on a tube structure of carbon atoms, which is a material of very high thermal conductivity, can effectively radiate heat of a very high generated in semiconductor elements, etc., such as transistors 24a, 24b, etc. Accordingly, the semiconductor device can have good heat radiation characteristics.
摘要翻译：半导体器件包括形成在半导体衬底10上的绝缘膜30a-30f和埋在绝缘膜中的热导体42。热导体形成在碳原子的管结构上。热导体形成在具有非常高导热性的材料的碳原子的管结构上，可以有效地辐射半导体元件等（诸如晶体管24a，24b等）中产生的非常高的热。因此，半导体器件可以具有良好的散热特性。

3. 发明授权

US06717192B2 Schottky gate field effect transistor 有权
标题翻译：肖特基门场效应晶体管
公开(公告)号：US06717192B2
公开(公告)日：2004-04-06
申请号：US10337107
申请日：2003-01-06
申请人： Yosuke Miyoshi
发明人： Yosuke Miyoshi
IPC分类号： H01L2980
CPC分类号： H01L29/42316 , H01L29/812
摘要： A Schottky gate FET including a gate electrode having a gate extension, a drain electrode and a drain contact layer overlying a semi-insulating substrate, wherein the gate extension overlies at least part of the drain electrode and the drain contact layer. The vertical overlapping between the gate extension and the drain contact region prevents the current reduction to make the circuit module mounting the Schottky gate FET non-usable.
摘要翻译：一种肖特基栅极FET，包括具有栅极延伸的栅电极，覆盖半绝缘衬底的漏电极和漏极接触层，其中栅极延伸部至少覆盖漏电极和漏极接触层的一部分。栅极延伸和漏极接触区域之间的垂直重叠可防止电流降低，使得安装肖特基栅极FET的电路模块不可用。

4. 发明授权

US06686616B1 Silicon carbide metal-semiconductor field effect transistors 有权
标题翻译：碳化硅金属半导体场效应晶体管
公开(公告)号：US06686616B1
公开(公告)日：2004-02-03
申请号：US09567717
申请日：2000-05-10
申请人： Scott T. Allen , John W. Palmour , Terrence S. Alcorn
发明人： Scott T. Allen , John W. Palmour , Terrence S. Alcorn
IPC分类号： H01L2980
CPC分类号： H01L29/8128 , H01L21/7605 , H01L29/1608 , H01L29/47 , H01L29/66068 , H01L29/66856 , H01L29/812
摘要： SiC MESFETs are disclosed which utilize a semi-insulating SiC substrate which substantially free of deep-level dopants. Utilization of the semi-insulating substrate may reduce back-gating effects in the MESFETs. Also provided are SiC MESFETs with a two recess gate structure. MESFETS with a selectively doped p-type buffer layer are also provided. Utilization of such a buffer layer may reduce output conductance by a factor of 3 and produce a 3 db increase in power gain over SiC MESFETs with conventional p-type buffer layers. A ground contact may also be provided to the p-type buffer layer and the p-type buffer layer may be made of two p-type layers with the layer formed on the substrate having a higher dopant concentration. SiC MESFETs according to embodiments of the present invention may also utilize chromium as a Schottky gate material. Furthermore, an oxide-nitride-oxide (ONO) passivation layer may be utilized to reduce surface effects in SiC MESFETs. Also, source and drain ohmic contacts may be formed directly on the n-type channel layer, thus, the n+ regions need not be fabricated and the steps associated with such fabrication may be eliminated from the fabrication process. Methods of fabricating such SiC MESFETs and gate structures for SiC FETs as well as passivation layers are also disclosed.
摘要翻译：公开了利用基本上不含深层掺杂剂的半绝缘SiC衬底的SiC MESFET。半绝缘衬底的利用可能会降低MESFET的反向栅极效应。还提供了具有两个凹陷栅极结构的SiC MESFET。还提供了具有选择性掺杂的p型缓冲层的MESFET。使用这种缓冲层可以将输出电导降低3倍，并且与传统的p型缓冲层相比，产生比SiC MESFET增加3db的功率增益。还可以向p型缓冲层提供接地触点，并且p型缓冲层可以由两层p型层制成，其中在衬底上形成的层具有较高的掺杂剂浓度。根据本发明实施例的SiC MESFET也可以使用铬作为肖特基栅极材料。此外，可以利用氧化物 - 氮化物 - 氧化物（ONO）钝化层来降低SiC MESFET中的表面效应。此外，源极和漏极欧姆接触可以直接形成在n型沟道层上，因此，不需要制造n +区，并且可以从制造过程中消除与这种制造相关联的步骤。还公开了制造这种SiC MESFET和用于SiC FET以及钝化层的栅极结构的方法。

5. 发明授权

US06630697B2 GaAs single crystal as well as method of producing the same, and semiconductor device utilizing the GaAs single crystal 失效
标题翻译： GaAs单晶及其制造方法以及利用GaAs单晶的半导体器件
公开(公告)号：US06630697B2
公开(公告)日：2003-10-07
申请号：US09911481
申请日：2001-07-25
申请人： Yoshihisa Fujisaki , Yukio Takano , Tsutomu Ishiba
发明人： Yoshihisa Fujisaki , Yukio Takano , Tsutomu Ishiba
IPC分类号： H01L2980
CPC分类号： H01L29/32 , C30B15/00 , C30B29/42 , H01L29/207 , H01L2924/0002 , H01L2924/00
摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.
摘要翻译：通过利用晶片中的晶格失真分布与场效应晶体管的阈值电压分布之间的强烈的相关性，晶片si中晶格畸变的分布减小，从而减轻半导体的特性分布晶片中的元素。将GaAs单晶在正常温度下的晶格畸变的最大值与最小值的差设定为4×10 -5以下，将GaAs单晶中所含的Si原子的密度设定为最多 1×10 16 cm -3，由此可以使其母材为GaAs单晶的半导体元件的特性均匀。

6. 发明授权

US06600181B2 Semiconductor integrated circuit and designing method thereof 失效
公开(公告)号：US06600181B2
公开(公告)日：2003-07-29
申请号：US09883318
申请日：2001-06-19
申请人： Shigenori Otake , Goichi Yokomizo , Shiro Kamohara
发明人： Shigenori Otake , Goichi Yokomizo , Shiro Kamohara
IPC分类号： H01L2980
CPC分类号： H01L23/66 , H01L23/3114 , H01L23/5227 , H01L23/5286 , H01L28/10 , H01L2924/0002 , H01L2924/19041 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit has a semiconductor internal circuit having a first power supply line and a second power supply line, wiring layers connected to a plurality of terminals of a first power supply and each having a predetermined inductance, and wiring layers connected to a plurality of terminals of a second power supply and each having a smaller inductance. Each of the former wiring layers has an inductor making a loop around the internal circuit.

7. 发明授权

US06586818B1 Self-aligned silicon germanium heterojunction bipolar transistor device with electrostatic discharge crevice cover for salicide displacement 有权
标题翻译：自对准硅锗异质结双极晶体管器件具有静电放电缝隙覆盖用于自动化位移
公开(公告)号：US06586818B1
公开(公告)日：2003-07-01
申请号：US09683986
申请日：2002-03-08
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L2980
CPC分类号： H01L29/66242 , H01L27/0251 , H01L29/7378
摘要： A method and structure for a bipolar transistor with a semiconductor substrate having a surface and a shallow trench isolation (STI) in the surface. The STI has an edge, a crevice region in the STI adjacent the STI edge, a base region above the STI, a silicide above the base region, an emitter structure on the surface adjacent the base region, and a crevice cover between the emitter structure and the silicide. The crevice cover maintains spacing between the emitter structure and the silicide.
摘要翻译：一种具有半导体衬底的双极晶体管的方法和结构，所述半导体衬底在表面具有表面和浅沟槽隔离（STI）。 STI具有边缘，邻近STI边缘的STI中的缝隙区域，STI上方的基极区域，基极区域上方的硅化物，与基极区域相邻的表面上的发射极结构，以及发射极结构和硅化物。缝隙盖保持发射极结构和硅化物之间的间距。

8. 发明授权

US06570199B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06570199B1
公开(公告)日：2003-05-27
申请号：US09679365
申请日：2000-10-05
申请人： Masanori Itoh
发明人： Masanori Itoh
IPC分类号： H01L2980
CPC分类号： H01P3/081 , H01L23/66 , H01L2924/0002 , H01P3/088 , H01L2924/00
摘要： A semiconductor device is provided which is capable of reducing direct current resistance in a signal line, of reducing a high-frequency resistance even in the case of transmitting high-frequency signals and, therefore, of increasing power gain when employed in, for example, an MMIC for high power. The semiconductor device has a microstrip line containing an interlayer dielectric and signal line formed on a semiconductor substrate on which predetermined circuit devices are mounted, wherein the signal line is made multi-layered with the interlayer dielectric interposed among the multiple layers and wherein the interlayer dielectric is made so thin that pin holes are produced and each layer constituting the signal line is electrically connected to each other through the pin holes.
摘要翻译：提供一种半导体器件，其能够降低信号线中的直流电阻，即使在发送高频信号的情况下也降低高频电阻，并且因此在例如采用高频信号时增加功率增益，用于高功率的MMIC。该半导体器件具有包含在其上安装有预定电路器件的半导体衬底上形成的层间电介质和信号线的微带线，其中信号线被多层层叠，并且其中层间电介质使得产生针孔并且构成信号线的每个层通过针孔彼此电连接。

9. 发明授权

US06566696B1 Self-aligned VT implant 有权
标题翻译：自对准VT植入
公开(公告)号：US06566696B1
公开(公告)日：2003-05-20
申请号：US09907359
申请日：2001-07-17
申请人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
发明人： Jon D. Cheek , Mark Michael , Derick J. Wristers , James F. Buller
IPC分类号： H01L2980
CPC分类号： H01L29/66583 , H01L29/105 , H01L29/66537 , H01L29/66545
摘要： Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type. Impurity grading across a source/drain-to-body junction is less abrupt, resulting in improved junction capacitance.
摘要翻译：提供了具有改善的结电容的晶体管的集成电路及其制造方法。一方面，提供一种制造方法，其包括在衬底的有源区中形成掺杂区域，其中所述掺杂区域具有第一导电类型和第一水平结。第一导电类型的第一源极/漏极区域形成在具有第二水平结的有源区域中。第一导电类型的第二源极/漏极区域在有源区域中形成有第三水平结和与限定沟道区域的第一源极/漏极区域的横向分离。第二和第三水平接头基本位于第一水平接头处。位于沟道区域中的掺杂区域的部分掺杂有与第一导电类型相反的第二导电类型的杂质。通过源极/漏极到体区结的杂质分级不太突然，导致改善的结电容。

10. 发明授权

US06559513B1 Field-plate MESFET 有权
标题翻译：现场板MESFET
公开(公告)号：US06559513B1
公开(公告)日：2003-05-06
申请号：US10127187
申请日：2002-04-22
申请人： Dain Curtis Miller , Inder J. Bahl , Edward L. Griffin
发明人： Dain Curtis Miller , Inder J. Bahl , Edward L. Griffin
IPC分类号： H01L2980
CPC分类号： H01L29/402 , H01L27/0605 , H01L29/812
摘要： A planar MESFET transistor includes a plurality of FET elements. Each FET element includes a doped planar channel, and source and drain coupled to the ends of the channel. A gate conductor extends over a portion of the channel at a location lying between the source and drain, a first predetermined distance from the drain. A field plate is connected to the gate conductor, and extends toward the drain a second predetermined distance, isolated from the channel except at its gate conductor connection by a dielectric material.
摘要翻译：平面MESFET晶体管包括多个FET元件。每个FET元件包括掺杂的平面沟道，以及耦合到沟道的端部的源极和漏极。栅极导体在位于源极和漏极之间的位置处延伸超过沟道的一部分，距离漏极的第一预定距离。场板连接到栅极导体，并且朝向漏极延伸第二预定距离，与沟道隔离，除了通过电介质材料的栅极导体连接之外。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式