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1. 发明授权

US10891557B2 Quantum computer hardware with reflectionless filters for thermalizing radio frequency signals 有权
公开(公告)号：US10891557B2
公开(公告)日：2021-01-12
申请号：US16788439
申请日：2020-02-12
申请人： International Business Machines Corporation
发明人： Peter Mueller , Thomas Morf
IPC分类号： G06N10/00 , H03K17/92 , H03H11/54 , H03H11/04 , H03F19/00
摘要： A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

2. 发明申请

US20180167055A1 APPARATUSES AND METHODS FOR CALIBRATING ADJUSTABLE IMPEDANCES OF A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180167055A1
公开(公告)日：2018-06-14
申请号：US15834892
申请日：2017-12-07
申请人： Micron Technology, Inc.
发明人： Dean Gans
IPC分类号： H03H11/28 , H03H11/54
CPC分类号： H03H11/28 , G11C7/10 , G11C29/025 , G11C29/028 , H03H11/54 , H03K19/0005
摘要： Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

3. 发明授权

US06933773B2 Integrated circuit 有权
公开(公告)号：US06933773B2
公开(公告)日：2005-08-23
申请号：US10673566
申请日：2003-09-30
申请人： Ulf Mattsson , Gordon Wilson
发明人： Ulf Mattsson , Gordon Wilson
IPC分类号： H03F3/68 , H03H11/54 , G06G7/12
CPC分类号： H03F3/68 , H03H11/54
摘要： An integrated circuit comprises a biasing circuit for maintaining the transconductance of a Gm cell constant. The integrated circuit comprises an on-chip constant voltage source and an on-chip constant current source. The on-chip constant current source has a connection for an external resistance, the value of the external resistance determining the current generated by the constant current source. The biasing circuit comprises means for providing a first fraction (β) of the current generated by the on-chip current source to bias the output of the Gm cell, and means for providing a second fraction (α) of the voltage generated by the on-chip voltage source to bias the input of the Gm cell. The transconductance of the Gm cell is controlled to be equal to the ratio of said fraction of the current generated by the on-chip current source to said fraction of the voltage generated by the on-chip voltage source.

4. 发明授权

US5636254A Signal processing delay circuit 失效
标题翻译：信号处理延迟电路
公开(公告)号：US5636254A
公开(公告)日：1997-06-03
申请号：US430534
申请日：1995-04-25
申请人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
发明人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , H03H11/26 , H03H11/54 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/00 , H04L7/02
CPC分类号： H03L7/0805 , G11B20/10 , G11B20/1403 , H03K5/13 , H03L7/0812 , H03L7/0896 , H03L7/0995 , H04L7/02 , H04L7/0008 , H04L7/0041
摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
摘要翻译：制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。数据采集电路和数据写入电路各自包括模拟可变延迟电路。

5. 发明授权

US3715609A Temperature compensation of voltage controlled resistor 失效
标题翻译：电压控制电阻的温度补偿
公开(公告)号：US3715609A
公开(公告)日：1973-02-06
申请号：US3715609D
申请日：1971-08-17
申请人： TEKTRONIX INC
发明人： HALLEN T
IPC分类号： H03F1/30 , H03F3/345 , H03G3/10 , H03H5/12 , H03H11/54 , H03K3/26
CPC分类号： H03F3/3455 , H03F1/302 , H03F1/306
摘要： A voltage controlled resistor of the junction gate field effect type is temperature compensated by a circuit including the emitter-base junction of a bipolar transistor and also a temperature responsive resistor having a temperature sensitivity which is substantially the same as that of the channel of the voltage controlled resistor. The temperature responsive resistor and the bipolar transistor are subjected to substantially the same temperature conditions as the voltage variable resistor and the voltage responsive resistor and emitter-base junction of the bipolar transistor are connected in series with a current source. The voltage drops across such emitter-base junction and voltage responsive resistor vary with such temperature and are employed as parts of a reverse-bias potential applied between the gate and channel of the voltage controlled resistor.
摘要翻译：结栅场效应型的电压控制电阻器由包括双极晶体管的发射极 - 基极结的电路以及具有与电压的通道基本上相同的温度灵敏度的温度响应电阻器进行温度补偿受控电阻。温度响应电阻器和双极晶体管经受与电压可变电阻器和双极晶体管的电压响应电阻器和发射极 - 基极结点电流源串联的基本相同的温度条件。这种发射极 - 基极结和电压响应电阻之间的电压降随着这种温度而变化，并且被用作施加在压控电阻器的栅极和沟道之间的反向偏置电位的一部分。

6. 发明授权

US10733523B2 Quantum computer hardware with reflectionless filters for thermalizing radio frequency signals 有权
公开(公告)号：US10733523B2
公开(公告)日：2020-08-04
申请号：US16686761
申请日：2019-11-18
申请人： International Business Machines Corporation
发明人： Peter Mueller , Thomas Morf
IPC分类号： G06N10/00 , H03H11/54 , H03H11/04 , H03K17/92 , H03F19/00
摘要： A quantum computer hardware apparatus may include a first stage, which is connected to one or more signal generators, and a second stage adapted to be cooled down at a lower temperature than the first stage. Superconducting qubits are arranged in the second stage. The signal generators are configured, each, to generate radio frequency (RF) signals to drive the qubits, in operation. The apparatus may further include an intermediate stage between the first stage and the second stage, wherein the intermediate stage comprises one or more coolable filters, the latter configured for thermalizing RF signals from the signal generators. Related methods for thermalizing radio frequency signals in a quantum computer hardware apparatus are also disclosed.

7. 发明申请

US20190334505A1 APPARATUSES AND METHODS FOR CALIBRATING ADJUSTABLE IMPEDANCES OF A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190334505A1
公开(公告)日：2019-10-31
申请号：US16505369
申请日：2019-07-08
申请人： Micron Technology, Inc.
发明人： Dean Gans
IPC分类号： H03H11/28 , H03H11/54 , G11C29/02 , G11C7/10 , H03K19/00
摘要： Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

8. 发明授权

US5878097A Signal processing delay circuit 失效
标题翻译：信号处理延迟电路
公开(公告)号：US5878097A
公开(公告)日：1999-03-02
申请号：US865704
申请日：1997-05-30
申请人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
发明人： Kenichi Hase , Ryutaro Horita , Kunio Watanabe , Yoshiteru Ishida , Takashi Nara , Hiroshi Kimura
IPC分类号： G11B5/09 , G11B20/10 , G11B20/14 , H03H11/26 , H03H11/54 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/089 , H03L7/099 , H04L7/00 , H04L7/02 , H04L25/36 , H04L25/40
CPC分类号： H03L7/0805 , G11B20/10 , G11B20/1403 , H03K5/13 , H03L7/0812 , H03L7/0896 , H03L7/0995 , H04L7/02 , H04L7/0008 , H04L7/0041
摘要： A signal processing delay circuit is fabricated as a semiconductor integration circuit to cope with increase in the data transfer speed and data recording and reproducing density on a recording medium. In the delay circuit, the amount of delay of a reference delay circuit of a delay PLL is controlled to take a fixed value independent of deviation in quality of the semiconductor circuit, change in power, and alteration in temperature. A control signal supervising the delay amount of the reference delay circuit is employed to control amounts of delay of input signals supplied to a window adjustment delay circuit of a window adjustment circuit and a T/2 generation delay circuit generating a synchronizing signal. Each of these delay circuits includes an analog variable delay circuit having the same configuration. The window adjustment delay circuit is supervised by a signal obtained by weighting the control signal by a D/A converter. A data acquisition circuit and a data write circuit each include an analog variable delay circuit.
摘要翻译：制造信号处理延迟电路作为半导体积分电路，以应对数据传送速度的增加和记录介质上的数据记录和再现密度。在延迟电路中，延迟PLL的参考延迟电路的延迟量被控制为独立于半导体电路的质量偏差，功率变化和温度变化的固定值。采用监视参考延迟电路的延迟量的控制信号来控制提供给窗口调整电路的窗口调整延迟电路的输入信号的延迟量和产生同步信号的T / 2产生延迟电路。这些延迟电路中的每一个包括具有相同配置的模拟可变延迟电路。窗口调整延迟电路由通过D / A转换器对控制信号进行加权而获得的信号进行监视。数据采集电路和数据写入电路各自包括模拟可变延迟电路。

9. 发明授权

US4967169A FET monolithic microwave integrated circuit variable slope gain-equalizer 失效
标题翻译： FET单片微波集成电路可变斜率增益均衡器
公开(公告)号：US4967169A
公开(公告)日：1990-10-30
申请号：US388094
申请日：1989-07-31
申请人： Horng-Jye Sun , Bruce C. Morley
发明人： Horng-Jye Sun , Bruce C. Morley
IPC分类号： H03F1/32 , H03H11/04 , H03H11/24 , H03H11/54
CPC分类号： H03H11/245 , H03F1/3241 , H03H11/04 , H03H11/54
摘要： A MMIC variable slope gain-equalizer varies the conductance of depletion mode Schottky gate FETs to controllably insert frequency dependent resonant members in a modified bridged-T configuration. Resistors connected from circuit input port to output port define the arms of the "T" and a T-node to which a first frequency dependent resonant member is connected in series with a first FET. A second FET and a second frequency dependent resonant member are each connected in series between the circuit ports, bridging the T. Preferably a third frequency dependent resonant member is series connected with the second frequency dependent member. Each frequency dependent resonant member resonates at about the highest frequency of interest, typically about 18 GHz. When the first FET is on and the second FET off, maximum attenuation at lower frequencies is inserted into the circuit, and when the first FET is off and the second FET on, minimum attenuation is inserted at lower frequencies. Intermediate levels of FET conductivity produce intermediate levels of frequency dependent attenuation. In a first embodiment, FET conductivity is controlled by two push-pull control voltages. A second embodiment uses a single control voltage to vary conductivity. The first embodiment operates at about 0-18 GHz, while the second embodiment operates at about 2-18 GHz. Each embodiment realizes a variable slope gain-versus frequency temperature function of between about -0.6 dB/GHz to about +0.2 dB/GHz with a 0 to +3VDC control voltage change.
摘要翻译： MMIC可变斜率增益均衡器改变耗尽型肖特基栅极FET的电导，以可变地插入经修改的桥接T配置中的频率相关谐振元件。从电路输入端口连接到输出端口的电阻器定义了与第一FET串联连接的第一频率相关谐振元件的“T”和T形节点的臂。第二FET和第二频率相关谐振元件各自串联在电路端口之间，桥接T。优选地，第三频率相关谐振元件与第二频率依赖元件串联连接。每个频率相关的谐振元件在大约最感兴趣的频率下谐振，通常约为18GHz。当第一个FET导通并且第二个FET关闭时，较低频率的最大衰减被插入到电路中，当第一个FET关闭并且第二个FET导通时，在较低的频率插入最小的衰减。中等水平的FET电导率产生中等水平的频率相关衰减。在第一实施例中，FET电导率由两个推挽控制电压控制。第二实施例使用单个控制电压来改变电导率。第一实施例在约0-18GHz下工作，而第二实施例在约2-18GHz下工作。每个实施例在0至+ 3VDC控制电压变化之间实现约-0.6dB / GHz至约+0.2dB / GHz的可变斜率增益对频率温度函数。

10. 发明授权

US4271366A Analog signal delay circuit 失效
标题翻译：模拟信号延迟电路
公开(公告)号：US4271366A
公开(公告)日：1981-06-02
申请号：US4484
申请日：1979-01-18
申请人： Takuro Isayama , Takeshi Takemoto , Tsutomu Sato , Takao Fukazawa
发明人： Takuro Isayama , Takeshi Takemoto , Tsutomu Sato , Takao Fukazawa
IPC分类号： H03H11/26 , H03H11/54 , H03K5/14 , H04N9/64 , H03K5/159 , H03K17/16 , H03K17/687
CPC分类号： H03H11/54 , H03K5/14
摘要： An analog delay circuit wherein an analog signal to be delayed as well as a reference voltage signal the voltage level of which is previously known are applied to an analog delay element comprising BBD, CCD or the like, and the reference signal is derived from the output of the analog delay element so that the reference signal or a signal associated therewith may be used for controlling a voltage to be applied to the analog element so as to set a bias voltage thereof.
摘要翻译：一种模拟延迟电路，其中要延迟的模拟信号以及其电压电平被预先知道的参考电压信号被施加到包括BBD，CCD等的模拟延迟元件，并且参考信号从输出模拟延迟元件，使得参考信号或与其相关联的信号可以用于控制要施加到模拟元件的电压，以便设置其偏置电压。

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