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1. 发明申请

US20210099080A1 INDUCTOR CURRENT EMULATOR CIRCUIT AND INDUCTOR CURRENT EMULATION METHOD 有权
公开(公告)号：US20210099080A1
公开(公告)日：2021-04-01
申请号：US16924981
申请日：2020-07-09
申请人： RICHTEK TECHNOLOGY CORPORATION
发明人： Hsuan-Ju Chen
IPC分类号： H02M3/155 , H03F3/45 , H03K4/00
摘要： An inductor current emulator circuit includes a ramp signal generation circuit and an emulator control circuit. The inductor emulator circuit generates a ramp signal for emulating an inductor current flowing through an inductor of a power stage circuit. The ramp signal generation circuit generates the ramp signal according to a first signal and a second signal. A current sense signal is related a high side switch current flowing through the high side switch or a low side switch current flowing through the low side switch. The emulator control circuit obtains a first difference integration value and a second difference integration value of differences between the current sense signal and the ramp signal during a first duration and a second duration, respectively, to generate the first signal and the second signal, respectively. Center time points of the first duration and the second duration are different from each other.

2. 发明授权

US10700699B1 Voltage-mode DAC driver with programmable mode output units 有权
公开(公告)号：US10700699B1
公开(公告)日：2020-06-30
申请号：US16354542
申请日：2019-03-15
申请人： Aquantia Corporation
发明人： Joseph Briaire
IPC分类号： H03M1/80 , H03M1/68 , H03M1/06 , H04B1/403 , H03K4/00 , H03M1/66
摘要： A digital-to-analog converter (DAC) includes input circuitry to receive a digital word of N bits, and an array of N bit processing units disposed in parallel. Each of the N bit processing units includes first switch circuitry to generate a first output state based on a first value of a received one of the N bits, and second switch circuitry to generate a second output state based on a second value of the received one of the N bits. The DAC also includes selectively enabled third switch circuitry to generate a conditional third output state.A voltage-mode driver includes input circuitry to selectively receive one of N bits of a digital word. First switch circuitry generates a first output state based on a first value of the received one of the N bits. Second switch circuitry generates a second output state based on a second value of the received one of the N bits. Selectively enabled third switch circuitry generates a conditional third output state.

3. 发明授权

US10564217B2 Built-in self-test method and apparatus for single-pin crystal oscillators 有权
公开(公告)号：US10564217B2
公开(公告)日：2020-02-18
申请号：US15979995
申请日：2018-05-15
申请人： Arm Limited
发明人： Alexandru Aurelian Ciubotaru
IPC分类号： G01R31/02 , H03B5/36 , H03K3/0231 , G01R31/28 , H03K4/00
摘要： A built-in self-test (BIST) methodology and apparatus provide for testing and calibration of an integrated circuit oscillator circuit topology that uses a one-pin (a single-pin) external resonator. The method employs dedicated test circuitry, also referred to herein as BIST apparatus, for the pass/fail verification of both the active and passive building blocks of the oscillator. At the same time, the methodology ensures accurate calibration and matching of the capacitors using dedicated digital circuitry and algorithms.

4. 发明授权

US10044346B2 Low-power slew rate detector for edge rate control of an output power stage 有权
公开(公告)号：US10044346B2
公开(公告)日：2018-08-07
申请号：US15261500
申请日：2016-09-09
申请人： Nuvoton Technology Corporation
发明人： Peter J. Holzmann
IPC分类号： H03K17/16 , H03K4/00 , H03K5/12 , H03F3/45 , G05F3/02 , H03K17/687 , H03K5/04 , G11C27/02 , H03K7/08
摘要： A circuit for determining a slew rate of an input signal includes a first MOSFET, a second MOSFET, and a resistor coupled in series between a ground terminal and a power terminal. The resistor is coupled between the power terminal and the second MOSFET, and the first MOSFET is coupled between the second MOSFET and the ground. The second MOSFET is coupled to a bias circuit to provide a bias current. The circuit also includes a capacitor having a first terminal and a second terminal, the first terminal coupled to the input signal and the second terminal coupled to the gate terminal and the drain terminal of the first MOSFET. A current flowing through the MOSFET during changes in the input signal represents a slew rate of the input signal.

5. 发明申请

US20180191333A1 MULTI-PHASE CONTROL FOR PULSE WIDTH MODULATION POWER CONVERTERS 审中-公开
公开(公告)号：US20180191333A1
公开(公告)日：2018-07-05
申请号：US15398912
申请日：2017-01-05
申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
发明人： Gang CHEN , Gabor REIZIK
IPC分类号： H03K3/017 , H03K4/00 , H02M3/156 , H02M1/15
CPC分类号： H02M1/15 , H02M3/156 , H02M3/1584 , H02M2003/1586 , H03K7/08
摘要： A controller controls Pulse Width Modulation (PWM) signals of one or more phases. The controller includes a phase sequencer to select a phase, a common ramp generator generating a common ramp signal, a phase activation circuit to turn on the PWM signal of the selected phase based on the common ramp signal, and for each phase a Current Sense plus Ramp (CSR) signal generator to generate a phase CSR signal according to a current of the phase and a phase deactivation circuit to turn off the PWM signal of the phase based on the phase CSR signal. A method of controlling PWM phases comprises selecting a phase, generating a common ramp signal, turning on the PWM signal of the selected phase based on the common ramp signal, generating CSR signals according to currents of the phases, and turning off the PWM signals based on the respective CSR signals.

6. 发明申请

US20050134315A1 Output circuit 失效
标题翻译：输出电路
公开(公告)号：US20050134315A1
公开(公告)日：2005-06-23
申请号：US10967248
申请日：2004-10-19
申请人： Akihiro Nakahara , Osamu Souma
发明人： Akihiro Nakahara , Osamu Souma
IPC分类号： H02M1/08 , H03K4/00 , H03K17/04 , H03K17/0412 , H03K17/16 , H03K17/687 , H03K19/0175 , H03K19/094
CPC分类号： H03K17/163 , H03K4/00 , H03K17/04123
摘要： An output circuit comprises a source follower constituted by a n-channel MOS transistor, having a drain connected to a power source and a source connected to an output terminal, and applying an output voltage to a load through the output terminal when a gate is charged according to an inputted turn-on signal, a voltage detector determining if the output voltage is at a first voltage level substantially the same as a voltage level of the power source or at a second voltage level lower than the first voltage level, a first discharge circuit discharging the gate of the source follower according to an inputted turn-off signal when the output voltage is at the first voltage level, and stopping discharging the gate of the source follower when the output voltage decreases from the first voltage level to the second voltage level and a second discharge circuit discharging the gate of the source follower more gradually than the first discharge circuit does according to the turn-off signal when the output voltage decreases from the first voltage level to the second voltage level.
摘要翻译：输出电路包括由n沟道MOS晶体管构成的源极跟随器，漏极连接到电源和连接到输出端子的源极，并且当栅极被充电时通过输出端子向负载施加输出电压根据输入的导通信号，电压检测器确定输出电压是否处于与电源的电压电平基本相同的第一电压电平或者低于第一电压电平的第二电压电平，第一放电当输出电压处于第一电压电平时，根据输入的关断信号对源极跟随器的栅极进行放电，并且当输出电压从第一电压电平降低到第二电压时，停止对源极跟随器的栅极的放电电平和第二放电电路比第一放电电路逐渐地放电源极跟随器的栅极根据截止信号，当t 他将电压从第一电压电平输出到第二电压电平。

7. 发明申请

US20050024120A1 Method and apparatus for controlling a dual-slope integrator circuit to eliminate settling time effect 有权
标题翻译：用于控制双斜率积分器电路以消除稳定时间效应的方法和装置
公开(公告)号：US20050024120A1
公开(公告)日：2005-02-03
申请号：US10748580
申请日：2003-12-30
申请人： Tsin-Yuan Chang , Ming-Jun Hsiao , Jing-Reng Huang
发明人： Tsin-Yuan Chang , Ming-Jun Hsiao , Jing-Reng Huang
IPC分类号： G06F5/00 , G06G7/18 , G06G7/186 , H03K4/00 , H03K4/06 , H03K5/1534
CPC分类号： G06G7/186 , H03K4/066 , H03K5/1534
摘要： In a method and apparatus for controlling a dual-slope integrator circuit, a reset signal is provided to a reset input of the integrator circuit to maintain a reset state of an integrating capacitor for a predetermined reset time period in response to an original input signal. A delayed input signal is simultaneously generated by introducing a predetermined delay period into the original input signal, the delay period being longer than the reset time period. With reference to the original input signal and the delayed input signal, a trigger signal is provided to an integrator input of the integrator circuit for enabling charging operation of the integrating capacitor during a charging period that starts from the end of the reset time period and that terminates at a lagging edge of the delayed input signal.
摘要翻译：在用于控制双斜率积分器电路的方法和装置中，响应于原始输入信号，将复位信号提供给积分器电路的复位输入，以将积分电容器的复位状态保持在预定复位时间段。通过将预定的延迟周期引入原始输入信号中，延迟输入信号同时产生，延迟时间长于复位时间段。参考原始输入信号和延迟输入信号，将触发信号提供给积分器电路的积分器输入，用于在从复位时间段结束开始的充电期间内对积分电容器进行充电操作，在延迟输入信号的滞后沿终止。

8. 发明授权

US5633600A Output buffer circuit having a minimized output voltage propagation 失效
标题翻译：输出缓冲电路具有最小的输出电压传播
公开(公告)号：US5633600A
公开(公告)日：1997-05-27
申请号：US536780
申请日：1995-09-29
申请人： Yasuhiro Ohnishi
发明人： Yasuhiro Ohnishi
IPC分类号： H03K19/003 , H03K4/00 , H03K17/04 , H03K17/16 , H03K17/687 , H03K19/017 , H03K19/0175
CPC分类号： H03K17/162 , H03K4/00
摘要： In an output buffer circuit so configured that a capacitor connected to a gate of an output driving MOS transistor and including a gate capacitance of the output driving MOS transistor is gradually charged through a resistor, so as to realize a slow rising or falling time, there is additionally provided a threshold voltage charging circuit for rapidly charging the capacitor to a threshold voltage level of the output driving MOS transistor when the output driving MOS transistor is to be turned on. With this arrangement, the propagation delay time of an output voltage can be minimized.
摘要翻译：在输出缓冲器电路中，通过电阻器连接到输出驱动MOS晶体管的栅极并且包括输出驱动MOS晶体管的栅极电容的电容器逐渐充电，从而实现缓慢的上升或下降时间，另外设置有阈值电压充电电路，用于当输出驱动MOS晶体管导通时，将电容器快速充电至输出驱动MOS晶体管的阈值电压电平。通过这种布置，输出电压的传播延迟时间可以最小化。

9. 发明授权

US5581163A Generator of periodic signals 失效
标题翻译：周期信号发生器
公开(公告)号：US5581163A
公开(公告)日：1996-12-03
申请号：US464598
申请日：1995-06-05
申请人： Jader Alves de Lima , Yong-Uk Lee , Pierre J. Nunzi
发明人： Jader Alves de Lima , Yong-Uk Lee , Pierre J. Nunzi
IPC分类号： H04N5/06 , H03K3/64 , H03K3/72 , H03K3/78 , H03K4/00 , H04N3/233 , H04N5/44 , G09G1/04 , H01J29/70
CPC分类号： H03K3/78 , H03K3/64 , H03K4/00 , H04N3/2335
摘要： A periodic signal is produced by counting pulses of a clock during a given period of time. The number of pulses counted is divided by a whole number. A count is then made of the number of pulses of this clock whose number corresponds to the quotient of this division. At each batch, a value of a periodic signal is produced.
摘要翻译：通过在给定时间段内对时钟的脉冲进行计数来产生周期性信号。计数的脉冲数除以整数。然后计数该时钟的脉冲数，其数量对应于该除法的商。在每个批次中，产生周期性信号的值。

10. 发明授权

US5576634A Bus driver for high-speed data transmission with waveform adjusting means 失效
标题翻译：总线驱动器，用于通过波形调整装置进行高速数据传输
公开(公告)号：US5576634A
公开(公告)日：1996-11-19
申请号：US544581
申请日：1995-10-18
申请人： Hiroshi Kamiya
发明人： Hiroshi Kamiya
IPC分类号： G06F3/00 , H03K4/00 , H03K6/04 , H03K17/16 , H03K19/0175
CPC分类号： H03K4/00 , H03K17/16 , H03K6/04
摘要： A bus driver includes differentiating and delay circuits connected together in parallel. The differentiating circuit receives an input signal via a first buffer circuit and produces a first signal having a falling and rising period. The delay circuit delays the input signal to produce a second signal output via a second buffer circuit. The second signal is delayed so that the second signal begins falling after the first signal starts falling and so that second signal begins rising after the first signal starts rising. The first and second signals are combined to produce an output signal. The preceding edge of the output signal is rounded because the relatively short falling of the first signal precedes the relatively long falling of the second signal. The following edge of the output signal is rounded because the short rising of the first signal suppresses an end portion of the long falling of the second signal. The waveform of the output signal is adjustable by changing parameters such as, for example, the delay time of the delay circuit, the capacitance of the capacitor and the power of the first and second buffer circuits.
摘要翻译：总线驱动器包括并联连接在一起的差分和延迟电路。微分电路通过第一缓冲电路接收输入信号，并产生具有下降和上升周期的第一信号。延迟电路延迟输入信号以产生经由第二缓冲电路输出的第二信号。第二信号被延迟，使得第二信号在第一信号开始下降之后开始下降，从而第二信号在第一信号开始上升之后开始上升。第一和第二信号被组合以产生输出信号。由于第一信号的相对短的下降在第二信号的相对长的下降之前，所以输出信号的前沿被舍入。输出信号的下一个边缘被舍入，因为第一信号的短暂上升抑制了第二信号的长时间下降的一个端部。通过改变诸如延迟电路的延迟时间，电容器的电容和第一和第二缓冲电路的功率的参数来调节输出信号的波形。

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