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1. 发明授权

US11609744B2 Open/close counting device 有权
公开(公告)号：US11609744B2
公开(公告)日：2023-03-21
申请号：US17162942
申请日：2021-01-29
申请人： MATSUI MFG. CO., LTD.
发明人： Satoru Tojyo , Hironobu Matsui
IPC分类号： G06F7/62 , G06F3/14 , B29C45/76 , B29C33/00
摘要： An open/close counting device to be attached to one of a first die and a second die which constitute a die, the die being opened by relatively moving the first die and the second die, the open/close counting device counting the number of open/close times of the die. The open/close counting device includes an open/close detecting section provided so as to face a target face of the other of the first die and the second die and to detect relative displacement of the target face along a die moving direction in non-contact condition, and includes an output section to output the open/close times counted based on detection of open/close by the open/close detecting section.

2. 发明授权

US10679735B2 Computer-implemented tools for use in electrophysiology 有权
公开(公告)号：US10679735B2
公开(公告)日：2020-06-09
申请号：US16200770
申请日：2018-11-27
申请人： Maurice M. Klee
发明人： Maurice M. Klee
IPC分类号： G06F17/50 , G06F7/62 , G16C20/30 , G16H50/50 , G06F30/20 , G06F19/00
摘要： Improved computer-implemented tools for use in modeling/simulating spatial charge distributions for electrophysiological systems are provided. The improvements are in three areas: (1) the use of solid angles to calculate quantities of free charge and/or bound charge in calculation cells and/or the movement of quantities of free charge across one or more faces of a calculation cell; (2) the use of flattened calculations cells having only two faces with substantial areas as seen from the free charge and/or the bound charge of the electrophysiological system; and (3) the use of at least two spatial charge distributions, specifically, at least one for bound charge and at least one for free charge, so as to include the effects of relative dielectric constants greater than 1.0 for part or all of an electrophysiological system. The three improvements can be used individually or in combinations.

3. 发明申请

US20190332980A1 ANALYSIS METHOD, ANALYSIS APPARATUS, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM FOR STORING PROGRAM 审中-公开
公开(公告)号：US20190332980A1
公开(公告)日：2019-10-31
申请号：US16375882
申请日：2019-04-05
申请人： FUJITSU LIMITED
发明人： Tetsuya UCHIUMI , Yuji SAITO , Masahiro Asaoka , Reiko Kondo , YUKIHIRO WATANABE
IPC分类号： G06Q10/06 , G06N5/02 , G06F17/27 , G06F16/35 , G06F7/62 , G06K9/62 , G06K9/72
摘要： An analysis method includes: executing first accumulation processing for accumulating analysis reports including an analysis item regarding an analysis target and analysis results with respect to the analysis item; executing first extraction processing for extracting the analysis item and texts representing the analysis results from each of the analysis reports accumulated; executing first identification processing for identifying analysis techniques corresponding to the texts extracted; executing generation processing for generating analysis patterns; executing second identification processing for identifying first analysis patterns; executing third identification processing for identifying other analysis patterns; executing second accumulation processing for accumulating pattern information; executing second extraction processing for extracting the analysis item and the texts from a new analysis report; and executing output processing for identifying an analysis technique.

4. 发明申请

US20190034169A1 NON-VOLATILE COUNTER SYSTEM, COUNTER CIRCUIT AND POWER MANAGEMENT CIRCUIT WITH ISOLATED DYNAMIC BOOSTED SUPPLY 审中-公开
公开(公告)号：US20190034169A1
公开(公告)日：2019-01-31
申请号：US15828204
申请日：2017-11-30
申请人： Texas Instruments Incorporated
发明人： Sudhanshu KHANNA , Hao MENG , Michael ZWERG , Christy Leigh SHE , Steven Craig BARTLING
IPC分类号： G06F7/62 , H03K5/24 , G11C11/56 , G06F1/26 , G08C13/02
摘要： Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

5. 发明授权

US09154141B2 Continuous high-frequency event filter 有权
标题翻译：连续高频事件滤波器
公开(公告)号：US09154141B2
公开(公告)日：2015-10-06
申请号：US13294083
申请日：2011-11-10
申请人： Tyler Gomm , Kang Yong Kim
发明人： Tyler Gomm , Kang Yong Kim
IPC分类号： H03L7/08 , H03L7/081 , H03L7/085 , H03L7/089 , G11C7/22 , G06F7/62
CPC分类号： H03L7/0814 , G06F7/62 , G11C7/22 , G11C7/222 , H03L7/0805 , H03L7/085 , H03L7/089
摘要： A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.
摘要翻译：一种用于响应于由事件信号表示的N个事件来产生有效输出信号的电路和方法。计数器电路被配置为响应于事件信号递增和递减一系列值。耦合到计数器电路的检测逻辑被配置为检测序列的至少第一和第二值。检测逻辑还被配置为产生有效输出信号并且响应于检测到第一值而切换到检测第二值，并且产生有效输出信号并且响应于检测到第二值而切换到检测第一值。第一个值和第二个值用N个数值分隔。

6. 发明授权

US08484006B2 Method for dynamically adjusting speed versus accuracy of computer platform simulation 有权
标题翻译：动态调整计算机平台仿真速度与准确度的方法
公开(公告)号：US08484006B2
公开(公告)日：2013-07-09
申请号：US12819981
申请日：2010-06-21
申请人： Niels Vanspauwen , Tom Michiels , Karl Van Rompaey
发明人： Niels Vanspauwen , Tom Michiels , Karl Van Rompaey
IPC分类号： G06F17/50 , G06F7/62 , G06F9/44 , G06F13/10 , G06F9/45
CPC分类号： G06F17/5009 , G06F17/5022
摘要： Executing a simulation of a computer platform, the simulation including simulation models. A dynamic quantum is accessed whose current value specifies a maximum number of units of execution a simulation model is allowed to perform without synchronizing with another simulation model. The dynamic quantum may be received from a user. Respective simulation models are invoked for execution with the current value of the dynamic quantum provided to each of the simulation models. The method also comprises modifying the value of the dynamic quantum based on a simulation event.
摘要翻译：执行计算机平台的仿真，仿真包括仿真模型。访问动态量子，其当前值指定允许执行仿真模型的最大执行单位数，而不与另一个仿真模型同步。可以从用户接收动态量。使用提供给每个仿真模型的动态量程的当前值来调用相应的仿真模型来执行。该方法还包括基于模拟事件修改动态量子的值。

7. 发明授权

US08453080B2 Model build in the presence of a non-binding reference 失效
标题翻译：存在非绑定引用的模型构建
公开(公告)号：US08453080B2
公开(公告)日：2013-05-28
申请号：US12335766
申请日：2008-12-16
申请人： Wolfgang Roesner , Robert J. Shadowen , Derek E. Williams
发明人： Wolfgang Roesner , Robert J. Shadowen , Derek E. Williams
IPC分类号： G06F17/50 , G06F9/455 , G06F7/62
CPC分类号： G06F17/5045
摘要： One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.
摘要翻译：一个或多个硬件描述语言（HDL）文件描述了定义要仿真的数字设计的多个分层布置的设计实体以及不属于数字设计的多个配置实体，所述多个配置实体逻辑地控制数字的多个配置锁存器的设置设计。编译HDL文件以获得数字设计的模拟可执行模型和相关联的配置数据库。编译包括解析配置语句，该配置语句指定配置实体的实例与指定的配置锁存器之间的关联，确定在HDL文件中是否描述了指定的配置锁存器，以及如果不是，则创建指示配置数据库，配置锁存器的实例与其无法绑定到的配置锁存器具有指定的关联。

8. 发明授权

US07885798B2 Closed-loop modeling of gate leakage for fast simulators 有权
标题翻译：用于快速模拟器的栅极泄漏的闭环建模
公开(公告)号：US07885798B2
公开(公告)日：2011-02-08
申请号：US11746976
申请日：2007-05-10
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Ying Liu , Sani R. Nassif , Jayakumaran Sivagnaname
IPC分类号： G06F17/50 , G06F7/62
CPC分类号： G06F17/5036
摘要： A method for circuit simulation using a netlist in which a first device having an unmodeled, nonlinear behavior is modified by inserting a second device which has a nonlinear response approximating the unmodeled nonlinear behavior. The first device may be for example a first transistor and the second device may be a variable current source, in particular one whose current is modeled after a floating transistor template which represents gate leakage current of the first transistor (gate-to-source or gate-to-drain). During simulation of the circuit a parameter such as a gate-to-source voltage of the second transistor is controlled to model gate leakage. The model parameters can be a function of an effective quantum mechanical oxide thickness value of a gate of the first transistor technology.
摘要翻译：一种使用网表的电路仿真方法，其中具有未建模的非线性行为的第一器件通过插入具有接近未建模的非线性行为的非线性响应的第二器件而被修改。第一器件可以是例如第一晶体管，并且第二器件可以是可变电流源，特别是其中电流在表示第一晶体管（栅极至源极或栅极 -排水）。在仿真电路期间，控制诸如第二晶体管的栅极至源极电压的参数来模拟栅极泄漏。模型参数可以是第一晶体管技术的栅极的有效量子机械氧化物厚度值的函数。

9. 发明授权

US07636612B2 Method for optimizing the transport displacement of workpieces in transfer presses 失效
标题翻译：用于优化转印机中工件的输送位移的方法
公开(公告)号：US07636612B2
公开(公告)日：2009-12-22
申请号：US11943078
申请日：2007-11-20
申请人： Elmar Weber , Hermann Benkler
发明人： Elmar Weber , Hermann Benkler
IPC分类号： G06F19/00 , G05B19/18 , G06F7/62 , G06F9/44
CPC分类号： B21D43/05 , G05B19/4069 , G05B2219/40317 , G05B2219/45142
摘要： A simulation method for optimizing transport displacement of workpieces in transfer presses is provided. Conclusions relating to the freedom of motion, number of strokes and program data for tool-specific machine control are determined by manipulating a displacement curve on a digital image of the transfer press which is determined by the simulation method.
摘要翻译：提供了一种用于优化转印机中工件运输位移的模拟方法。通过操作由模拟方法确定的转印机的数字图像上的位移曲线来确定与工具自由度，笔画数量和程序数据有关的结论。

10. 发明授权

US07464287B2 Strategy to verify asynchronous links across chips 有权
标题翻译：跨芯片验证异步链接的策略
公开(公告)号：US07464287B2
公开(公告)日：2008-12-09
申请号：US10815903
申请日：2004-03-31
申请人： Debendra Das Sharma , Gurushankar Rajamani , Hanh Hoang
发明人： Debendra Das Sharma , Gurushankar Rajamani , Hanh Hoang
IPC分类号： G06F5/06 , G06F17/50 , G06F7/62
CPC分类号： H04L49/9078 , H04L49/90
摘要： Various embodiments of the invention provide a frequency shifter to vary the frequency of data transmitted over time, such as to increase and decrease the frequency of test data transmitted over time to verify a digital communication device's ability to receive data having various frequencies within a specific parameter range. The frequency shifter includes a frequency modifier to shift or vary an input clock frequency to a variety of output clock frequencies, such as according to a test protocol. The frequency shifter also includes an elastic data buffer to receive the test data at the input clock frequency and to output the test data at the plurality of output clock frequencies provided by the frequency modifier.
摘要翻译：本发明的各种实施例提供一种频率移位器来改变随时间传输的数据的频率，诸如增加和减少随时间传输的测试数据的频率，以验证数字通信设备接收具有特定参数内的各种频率的数据的能力范围。频移器包括频率修正器，用于将输入时钟频率移位或改变为各种输出时钟频率，例如根据测试协议。移相器还包括一个弹性数据缓冲器，用于以输入时钟频率接收测试数据，并输出由频率调节器提供的多个输出时钟频率的测试数据。

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