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1. 发明授权

US11410850B2 Aluminum oxide semiconductor manufacturing method and aluminum oxide semiconductor manufacturing device 有权
公开(公告)号：US11410850B2
公开(公告)日：2022-08-09
申请号：US17272869
申请日：2019-08-30
申请人： UACJ Corporation
发明人： Hiroki Arima , Koichi Ashizawa
IPC分类号： H01L21/00 , H01L21/24 , H01L21/40 , H01L21/42
摘要： A semiconductor manufacturing method by a semiconductor manufacturing device includes: positioning an anode, which causes an oxidation reaction, in a first end of a base material containing an aluminum oxide and a cathode, which causes a reduction reaction, in a second end of the base material; heating the base material to melt it with the anode being in contact with the first end of the base material and the cathode being in contact with the second end of the base material; causing a current to flow between the anode and the cathode to cause a molten salt electrolysis reaction for a whole of or a part of a period in which the base material is at least partially melted; and after the molten salt electrolysis reaction, cooling the base material to form a p-type aluminum oxide semiconductor layer and an n-type aluminum oxide semiconductor layer.

2. 发明申请

US20210272810A1 SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING DEVICE 有权
公开(公告)号：US20210272810A1
公开(公告)日：2021-09-02
申请号：US17272869
申请日：2019-08-30
申请人： UACJ Corporation
发明人： Hiroki Arima , Koichi Ashizawa
IPC分类号： H01L21/24 , H01L21/40 , H01L21/42
摘要： A semiconductor manufacturing method by a semiconductor manufacturing device includes: positioning an anode, which causes an oxidation reaction, in a first end of a base material containing an aluminum oxide and a cathode, which causes a reduction reaction, in a second end of the base material; heating the base material to melt it with the anode being in contact with the first end of the base material and the cathode being in contact with the second end of the base material; causing a current to flow between the anode and the cathode to cause a molten salt electrolysis reaction for a whole of or a part of a period in which the base material is at least partially melted; and after the molten salt electrolysis reaction, cooling the base material to form a p-type aluminum oxide semiconductor layer and an n-type aluminum oxide semiconductor layer.

3. 发明授权

US10903087B2 Laser processing method 有权
公开(公告)号：US10903087B2
公开(公告)日：2021-01-26
申请号：US16599809
申请日：2019-10-11
申请人： DISCO CORPORATION
发明人： Hiroshi Morikazu
IPC分类号： H01L21/42 , H01L21/428
摘要： A laser processing method for processing a substrate having a device formed on the front side, an electrode pad being formed on the device. The method includes applying a pulsed laser beam to the back side of the substrate at a position corresponding to the electrode pad, thereby forming a fine hole in the substrate so that the fine hole reaches the electrode pad, detecting first plasma light generated from the substrate by the application of the pulsed laser beam to the substrate and also detecting second plasma light generated from the electrode pad by the application of the pulsed laser beam to the electrode pad, and stopping the laser beam when the second plasma light is detected. Time intervals of the pulsed laser beam repeatedly applied to the same fine hole are set to 0.1 ms or more.

4. 发明申请

US20200027989A1 RADIATION HARDENED THIN-FILM TRANSISTORS 审中-公开
公开(公告)号：US20200027989A1
公开(公告)日：2020-01-23
申请号：US16457284
申请日：2019-06-28
申请人： Auburn University
发明人： Minseo Park , Michael C. Hamilton , Shiqiang Wang , Kosala Yapa Bandara
IPC分类号： H01L29/786 , H01L21/477 , H01L21/42 , H01L21/768
摘要： A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.

5. 发明申请

US20180097117A1 THIN-FILM TRANSISTOR, LIQUID CRYSTAL DISPLAY PANEL, AND THIN-FILM TRANSISTOR MANUFACTURING METHOD 审中-公开
公开(公告)号：US20180097117A1
公开(公告)日：2018-04-05
申请号：US15100402
申请日：2016-03-31
申请人： Shenzhen China Star Optoectronics Technology Co., Ltd.
发明人： Xiaobo HU
IPC分类号： H01L29/786 , G02F1/1368 , H01L21/42 , H01L29/66
CPC分类号： H01L29/78618 , G02F1/1368 , H01L21/42 , H01L27/124 , H01L29/41733 , H01L29/423 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： A thin-film transistor, a liquid crystal display panel, and a thin-film transistor manufacturing method are provided. The thin-film transistor includes a base plate and a gate electrode, a gate insulation layer, a source electrode, a drain electrode, a channel layer, first and second ohmic contact layers, a passivation layer, and a pixel electrode that are arranged on the same side of the base plate. The gate insulation layer covers the gate electrode that is on the base plate. The source electrode, the drain electrode, the channel layer, the first and second ohmic contact layers are arranged on the gate insulation layer. The channel layer is arranged between the source electrode and the drain electrode and corresponds to the gate electrode. The first ohmic contact layer is arranged between the source electrode and the channel layer. The second ohmic contact layer is arranged between the drain electrode and the channel layer.

6. 发明授权

US09111860B2 Ion implantation system and method 有权
标题翻译：离子注入系统及方法
公开(公告)号：US09111860B2
公开(公告)日：2015-08-18
申请号：US14452192
申请日：2014-08-05
申请人： Advanced Technology Materials, Inc.
发明人： Edward E. Jones , Sharad N. Yedave , Ying Tang , Barry Lewis Chambers , Robert Kaim , Joseph D. Sweeney , Oleg Byl , Peng Zou
IPC分类号： H01L21/26 , H01L21/42 , H01L21/265 , H01J37/08 , H01J37/317 , C23C14/48 , C23C14/52
CPC分类号： H01L21/265 , C23C14/48 , C23C14/52 , H01J37/08 , H01J37/3171 , H01J37/32055 , H01J37/32412 , H01J37/32449 , H01J2237/006 , H01J2237/022
摘要： An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system.
摘要翻译：一种离子注入系统和方法，用于提供掺杂剂气体进料管线中的掺杂气体的冷却，以通过例如使用诸如B2F4的硼源材料或BF3的其他替代物来通过电弧室发热来防止掺杂气体的加热和分解。描述了各种电弧室热管理布置，以及等离子体性能，特定流量布置，清洁过程，功率管理，平衡偏移，提取光学优化，流路中沉积物的检测和源寿命优化等方面的改进，以实现高效率离子注入系统的操作。

7. 发明授权

US08927419B2 Chip comprising an integrated circuit, fabrication method and method for locally rendering a carbonic layer conductive 有权
标题翻译：芯片包括用于局部渲染碳层导电的集成电路，制造方法和方法
公开(公告)号：US08927419B2
公开(公告)日：2015-01-06
申请号：US14078104
申请日：2013-11-12
申请人： Infineon Technologies AG
发明人： Uwe Hoeckele
IPC分类号： H01L21/4763 , H01L21/26 , H01L21/42 , H01L21/768 , H01L45/00 , H01L21/02 , H01L23/532
CPC分类号： H01L21/76886 , H01L21/0237 , H01L21/02444 , H01L21/02527 , H01L21/02675 , H01L21/76823 , H01L21/76838 , H01L21/76867 , H01L23/53276 , H01L45/149 , H01L2221/1094 , H01L2924/0002 , Y10S977/81 , H01L2924/00
摘要： A method can be used for locally rendering a carbonic isolating layer conductive. In one embodiment, a laser beam is directed onto the carbonic isolating layer so as to convert amorphous carbon of the carbonic isolating layer into graphite-like carbon. In another embodiment, the carbonic layer is heated so as to form a conducting portion of the layer so that a lateral path through the conducting portion connects two circuit elements of the integrated circuit.
摘要翻译：一种方法可以用于局部渲染碳隔离层导电。在一个实施例中，激光束被引导到碳隔离层上，以将碳隔离层的无定形碳转变为石墨状碳。在另一个实施例中，加热碳层以形成该层的导电部分，使得穿过导电部分的横向路径连接集成电路的两个电路元件。

8. 发明授权

US08912104B1 Method for fabricating integrated circuits with patterned thermal adjustment layers for design optimization 有权
标题翻译：具有图案化热调节层的集成电路的设计优化方法
公开(公告)号：US08912104B1
公开(公告)日：2014-12-16
申请号：US13047664
申请日：2011-03-14
申请人： Deepa Ratakonda , Christopher J. Pass , Che Ta Hsu , Fangyun Richter , Wilson Wong
发明人： Deepa Ratakonda , Christopher J. Pass , Che Ta Hsu , Fangyun Richter , Wilson Wong
IPC分类号： H01L21/26 , H01L21/324 , H01L21/42 , H01L21/477
CPC分类号： H01L29/6659 , H01L21/2686 , H01L21/324 , H01L21/823412 , H01L21/823418
摘要： An integrated circuit may include a substrate in which transistors are formed. The transistors may be associated with blocks of circuitry. Some of the blocks of circuitry may be configured to reduce leakage current. A selected subset of the blocks of circuitry may be selectively heated to reduce the channel length of their transistors through dopant diffusion and thereby strengthen those blocks of circuitry relative to the other blocks of circuitry. Selective heating may be implemented by coating the blocks of circuitry on the integrated circuit with a patterned layer of material such as a patterned anti-reflection coating formed of amorphous carbon or a reflective coating. During application of infrared light, the coated and uncoated areas will rise to different temperatures, selectively strengthening desired blocks of circuitry on the integrated circuit.
摘要翻译：集成电路可以包括其中形成晶体管的衬底。晶体管可以与电路块相关联。一些电路块可被配置为减少漏电流。可以选择性地加热电路块的选定子集，以通过掺杂剂扩散减小其晶体管的沟道长度，从而加强相对于其它电路块的那些电路块。选择性加热可以通过用图案化的材料层（例如由无定形碳或反射涂层形成的图案化抗反射涂层）涂覆集成电路上的电路块来实现。在应用红外光时，涂层和未涂覆的区域将升高到不同的温度，有选择地加强集成电路上所需的电路块。

9. 发明授权

US08900899B2 Method for production of optical waveguides and coupling and devices made from the same 有权
标题翻译：用于生产光波导和耦合的方法及由其制成的器件
公开(公告)号：US08900899B2
公开(公告)日：2014-12-02
申请号：US13931530
申请日：2013-06-28
申请人： Payam Rabiei
发明人： Payam Rabiei
IPC分类号： H01L21/00 , H01L21/4763 , H01L21/44 , H01L21/26 , H01L21/42 , H01L21/28 , H01L21/02 , H01L21/70 , H01L29/78 , G02B6/13 , G02B6/136 , G02B6/122 , G02B6/12
CPC分类号： G02B6/13 , B82Y20/00 , G02B6/1223 , G02B6/136 , G02B2006/1204 , G02B2006/12045 , G02B2006/12054 , G02B2006/12057 , G02B2006/12097
摘要： Novel processing methods for production of high-refractive index contrast and low loss optical waveguides are disclosed. In one embodiment, a “channel” waveguide is produced by first depositing a lower cladding material layer with a low refractive index on a base substrate, a refractory metal layer, and a top diffusion barrier layer. Then, a trench is formed with an open surface to the refractory metal layer. The open surface is subsequently oxidized to form an oxidized refractory metal region, and the top diffusion barrier layer and the non-oxidized refractory metal region are removed. Then, a low-refractive-index top cladding layer is deposited on this waveguide structure to encapsulate the oxidized refractory metal region. In another embodiment, a “ridge” waveguide is produced by using similar process steps with an added step of depositing a high-refractive-index material layer and an optional optically-transparent layer.
摘要翻译：公开了用于生产高折射率对比度和低损耗光波导的新型加工方法。在一个实施例中，通过在基底衬底，难熔金属层和顶部扩散阻挡层上首先沉积具有低折射率的下覆层材料层来制造“通道”波导。然后，形成具有开口表面的难熔金属层的沟槽。随后将开放的表面氧化以形成氧化的难熔金属区域，并且去除顶部扩散阻挡层和未氧化的难熔金属区域。然后，在该波导结构上沉积低折射率顶层，以封装氧化的难熔金属区域。在另一个实施例中，通过使用类似的工艺步骤，通过沉积高折射率材料层和可选的光学透明层的附加步骤来制造“脊”波导。

10. 发明授权

US08841157B2 Method and structure for using discontinuous laser scribe lines 有权
标题翻译：使用不连续激光划线的方法和结构
公开(公告)号：US08841157B2
公开(公告)日：2014-09-23
申请号：US13343546
申请日：2012-01-04
申请人： Matthew Rekow
发明人： Matthew Rekow
IPC分类号： H01L21/00 , H01L31/0224 , H01L27/142 , H01L21/42
CPC分类号： H01L31/022425 , H01L21/42 , H01L31/022458 , H01L31/046 , H01L31/0463 , Y02E10/50
摘要： A thin film photovoltaic device includes a substrate and a first conductive layer coupled to the substrate. The first conductive layer includes at least one first groove extending through a first portion of the first conductive layer to a portion of the substrate. The device also includes at least one semiconductor layer coupled to a remaining portion of the first conductive layer and the portion of the substrate. The at least one semiconductor layer includes a plurality of non-overlapping vias, each via extending through a portion of the at least one semiconductor layer to a portion of the first conductive layer. The device further includes a second conductive layer coupled to a remaining portion of the at least one semiconductor layer and portions of the first conductive layer. The second conductive layer includes at least one second groove extending through a portion of the second conductive layer to a portion of the at least one semiconductor layer.
摘要翻译：薄膜光伏器件包括衬底和耦合到衬底的第一导电层。第一导电层包括延伸穿过第一导电层的第一部分至基底的一部分的至少一个第一凹槽。该器件还包括耦合到第一导电层的剩余部分和衬底部分的至少一个半导体层。所述至少一个半导体层包括多个非重叠的通孔，每个通孔延伸穿过所述至少一个半导体层的一部分到所述第一导电层的一部分。该器件还包括耦合到至少一个半导体层的剩余部分和第一导电层的部分的第二导电层。第二导电层包括延伸穿过第二导电层的一部分至少一个半导体层的一部分的至少一个第二凹槽。

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