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1. 发明授权

US11637550B2 Clock selector circuit 有权
公开(公告)号：US11637550B2
公开(公告)日：2023-04-25
申请号：US17685288
申请日：2022-03-02
申请人： Nordic Semiconductor ASA
发明人： Simon Berg
IPC分类号： H03K5/01 , H03K5/135 , G06F1/08 , H03K4/02
摘要： A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.

2. 发明授权

US11626865B1 Low-power high-speed CMOS clock generation circuit 有权
公开(公告)号：US11626865B1
公开(公告)日：2023-04-11
申请号：US17481666
申请日：2021-09-22
申请人： QUALCOMM Incorporated
发明人： Jianwen Ye , Bo Sun , Cheng Zhong
IPC分类号： H03K5/01 , H03K19/20 , H03L7/081 , H03K5/00 , H04B1/40 , H04L12/40
摘要： A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

3. 发明授权

US11616492B1 Time-adaptive RF hybrid filter structures 有权
公开(公告)号：US11616492B1
公开(公告)日：2023-03-28
申请号：US17538171
申请日：2021-11-30
申请人： L3Harris Technologies, Inc.
发明人： Janez Jeraj , Patrick M. Ryan , Osama S. Haddadin
IPC分类号： H03K5/00 , H03H17/02 , H03K5/01 , H03H17/00
摘要： A digitally controlled analog filter device. The digitally controlled analog filter device includes one or more digitally controlled analog signal amplifiers. The digitally controlled analog signal amplifiers are configured to have a gain of the digitally controlled analog signal amplifiers controlled by digital signals. The digitally controlled analog filter device further includes one or more analog time delay circuits coupled to signal input nodes of the digitally controlled analog signal amplifiers. The analog time delay circuits are configured to implement an analog signal delay. The digitally controlled analog filter device further includes a digital closed loop control circuit coupled to the digitally controlled analog signal amplifiers to digitally control the gain of the digitally controlled analog signal amplifiers.

4. 发明申请

US20230087145A1 LOW-POWER HIGH-SPEED CMOS CLOCK GENERATION CIRCUIT 有权
公开(公告)号：US20230087145A1
公开(公告)日：2023-03-23
申请号：US17481666
申请日：2021-09-22
申请人： QUALCOMM Incorporated
发明人： Jianwen YE , Bo SUN , Cheng ZHONG
IPC分类号： H03K5/00 , H03K5/01 , H03K19/20 , H03L7/081 , H04B1/40 , H04L12/40
摘要： A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

5. 发明申请

US20230054999A1 LOW POWER WIDEBAND MULTITONE GENERATOR 有权
公开(公告)号：US20230054999A1
公开(公告)日：2023-02-23
申请号：US17407694
申请日：2021-08-20
申请人： International Business Machines Corporation
发明人： Sudipto Chakraborty , GEORGE Russell ZETTLES, IV , Daniel Ramirez
IPC分类号： G01R27/28 , H03M1/66 , H03K5/01
摘要： Systems, devices, computer-implemented methods, and/or computer program products that facilitate low power, wideband multitone generation. In one example, a multitone generator device can comprise a controller operatively coupled to first and second digital-to-analog converters (DACs). The controller can apply different delays of a sampling signal to the first and second DACs to facilitate sideband suppression of signals output by the first and second DACs. One aspect of such a multitone generator device is that the multitone generator device can facilitate low power, wideband multitone generation.

6. 发明授权

US11569804B1 INL detection and calibration for phase-interpolator 有权
公开(公告)号：US11569804B1
公开(公告)日：2023-01-31
申请号：US17727110
申请日：2022-04-22
申请人： Avago Technologies International Sales Pte. Limited
发明人： Seong-Ho Lee , SangHye Chung , Hyung-Joon Jeon , Vadim Milirud , Wei Zhang , Angus Tang
IPC分类号： H03K5/13 , H03K5/01 , H03K5/00
摘要： An apparatus includes control logic coupled to a phase detector circuit and an adjustable delay circuit. The control logic is configured to obtain a state of a first phase of an output signal of a phase interpolator relative to a second phase of a reference signal, and adjust a delay of the reference signal until the second phase matches the first phase. The control logic is further configured to measure a total delay of the reference signal when the second phase matches the first phase, and determine integral non-linearity of the phase interpolator at the first code based on the total delay. The control logic may further calibrate a first code of a phase interpolator based, at least in part, on the integral non-linearity.

7. 发明授权

US11569803B2 Stagger signal generation circuit 有权
公开(公告)号：US11569803B2
公开(公告)日：2023-01-31
申请号：US17666750
申请日：2022-02-08
申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.
发明人： Jia Wang
IPC分类号： H03K5/01 , H03K3/037 , H03K5/00
摘要： A stagger signal generation circuit is provided. The stagger signal generation circuit includes: a stagger pulse generation circuit, configured to generate a first pulse signal according to a first control signal and generate a second pulse signal according to a second control signal, the first control signal and the second control signal being inverted signals, and the first pulse signal and the second pulse signal being stagger pulse signals; and a delay signal output circuit including G signal output circuits, G being an integer greater than or equal to 2. Each non-first-stage signal output circuits receives a delay output signal outputted by a respective previous-stage signal output circuit as an input signal of a current-stage signal output circuit, and a first-stage signal output circuit receives an initial input signal as an input signal of the first-stage signal output circuit.

8. 发明授权

US11569802B1 Temperature delay device and temperature control system 有权
公开(公告)号：US11569802B1
公开(公告)日：2023-01-31
申请号：US17448527
申请日：2021-09-23
申请人： NANYA TECHNOLOGY CORPORATION
发明人： Wu-Der Yang
IPC分类号： H03K3/00 , H03K5/01 , H03K3/037 , G01K3/08 , H03K19/20 , H03K5/00
摘要： A temperature delay device includes a first thermal sensor, a second thermal sensor, an inverter, and a latch circuit. The first thermal sensor is configured to measure a first temperature of a chip to output a first input signal. The second thermal sensor is configured to measure a second temperature of the chip to output a second input signal. The inverter is coupled to the first thermal sensor, and is configured to reverse the first input signal so as to output a third input signal. The latch circuit is coupled to the inverter and the second thermal sensor, and is configured to output an output signal according to the second input signal and the third input signal. The first temperature is different from the second temperature.

9. 发明申请

US20230009665A1 SIGNAL PROCESSING CIRCUIT 有权
公开(公告)号：US20230009665A1
公开(公告)日：2023-01-12
申请号：US17716472
申请日：2022-04-08
申请人： FUJITSU LIMITED
发明人： Yoichi Kawano
IPC分类号： H03G3/30 , H03K5/01
摘要： A signal processing circuit includes a signal path for outputting a first signal included in an input signal from a first output terminal to another signal processor; branch paths one of which extends from a top position located at a position on the signal path and the others which extend from associated branch positions that divide the signal path starting from the top position to the first output terminal into segments in each of which a first amount of delay obtained by equally dividing an amount of delay caused by the signal path and that is added to the first signal; a switch connected to each of the branch paths and switches whether to allow a second signal other than the first signal included in the input signal to pass through the connected branch paths; a variable gain amplifier connected to each of the switches and amplifies the second signal.

10. 发明申请

US20220404858A1 IMPEDANCE MEASUREMENT CIRCUIT AND IMPEDANCE MEASUREMENT METHOD THEREOF 有权
公开(公告)号：US20220404858A1
公开(公告)日：2022-12-22
申请号：US17351248
申请日：2021-06-18
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Che Lu , Chin-Ming Fu , Chih-Hsien Chang
IPC分类号： G06F1/10 , H03K19/21 , H03K5/01 , G01R27/02
摘要： An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.

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