求和放大器相关的专利数据

序号	专利名	申请号	申请日	公开（公告）号	公开（公告）日	发明人
1	Summing amplifier	US108857	1979-12-31	US4311929A	1982-01-19	William L. Konrad; William L. Clay
A summing amplifier which sums and amplifies two input signals and combines them in a single load or output device. It includes a bridge circuit using either 4 NPN or 4 PNP type transistors. Two transformers are used to achieve input relationship. A square wave of different frequency is applied to each of the two input terminals and the sum of the two input frequencies is converted to a three level waveform of constant amplitude but with on-time variations periodic at the difference frequency of the two input frequencies.
2	Summing amplifier	US39133141	1941-05-01	US2401779A	1946-06-11	SWARTZEL JR KARL D

3	Summing power amplifier	US10873742	2004-06-21	US07157965B1	2007-01-02	Beomsup Kim
A power amplifier comprises an amplification stage comprises a plurality of amplifiers, wherein each amplifier provides an amplified output, and an inductive summing device configured to receive the plurality of amplified outputs and provide a combined output signal. A method of amplifying a signal comprises applying the signal to an amplifier stage comprising a plurality of amplifiers, wherein each amplifier is configured to provide an amplified output, and providing a combined output signal via an inductive summing device configured to receive the plurality of amplified outputs.
4	High performance summing amplifier	US15563	1979-02-26	US4268798A	1981-05-19	Elwood C. Reichart
A bipolar transistor is utilized as the feedback element of an inverting amplifier. The base of the transistor is connected to the amplifier's output, with the emitter connected to the input thereby providing 100% voltage feedback. The output is taken across the collector load of the transistor. Signal inputs to the amplifier are coupled through conventional summing resistors. The resulting configuration is capable of high frequency operation and provides excellent isolation between input signals.
5	Summing amplifier and method thereof	US14659676	2015-03-17	US09590560B2	2017-03-07	Chia-Liang (Leon) Lin
An apparatus includes: a first transconductance device of a first type configured to convert a first voltage into a first current of an output node; a second transconductance device of a second type configured to convert a second voltage into a second current of the output node; a common mode feedback circuit coupled to the output node configured to control a mean voltage at the output node in accordance with a reference voltage; and a reset circuit configured to reset a voltage at the output node in accordance with a clock signal.
6	Switched capacitor summing amplifier	US913424	1986-09-30	US4760346A	1988-07-26	Michael A. Kultgen; Danny T. Pinckley
A switch capacitor summing amplifier is disclosed having a coupling means to couple desired signals to the active amplifier in response to an enable signal. The coupling is performed in synchronism to the "odd" phase of the sampling signals thereby improving noise, transient and DC offset performance while minimizing switch impedance sensitivity.
7	Vector summation power amplifier	US390096	1982-06-21	US4575811A	1986-03-11	Russell E. Hammond; John L. Henry
A time sequence of square waves is summed to provide minimum distortion h power voltage sinusoids. The phase difference of two identical sinusoids is varied to control the resultant summed amplitude. Amplitude modulation of the sum sinusoid is achieved through varying the phase relationship between the two identical sinusoids. Frequency and phase modulation is achieved through digital control of the individual square waves.
8	오티에이를 이용하는 가산회로	KR1020080014021	2008-02-15	KR100953304B1	2010-04-20	남현석; 노정진
오티에이 회로가 채용된 아날로그 가산회로가 개시된다. 입력부의 게이트 단자로 인가된 입력신호는 각각의 출력 노드에 전압의 형태로 나타난다. 오티에이의 음의 입력 단자에 연결된 저항을 통해 전달되는 전류는 출력 스테이지로 흐른다. 또한, 바이어스부에서 생성된 바이어스 전류는 출력 스테이지를 흐르며, 출력 스테이지의 저항을 흐르는 전류에 의해 출력 전압이 형성된다. 입력부에 연결된 오티에이 회로의 채용에 의해 입력 임피던스는 상승하며, 출력단자에서 바라보는 출력저항도 상승한다. 따라서, 입력의 범위 상승되더라도 정상적인 동작을 수행할 수 있으며, 정확한 가산동작을 수행할 수 있는 가산회로를 구성할 수 있다. 연산 증폭기, 가산기, 오티에이
9	Summing amplifier with a complex weighting factor and interface including such a summing amplifier	US632963	1990-12-20	US5293421A	1994-03-08	Hans-Jurgen Zanzig
Summing amplifiers may be constructed from feedback operational amplifiers. The weighting factors are quotients of the feedback resistance common to all quantities to be summed and the individual dropping resistances. Only the feedback resistance has a directly proportional effect, while the effects of the individual dropping resistances are inversely proportional. The formation of specified complex weighting factors is difficult, especially if the summing amplifier is intended for use in a two-wire/four-wire interface between a subscriber line and a telecommunications network and is to be mass produced at low cost as an integrated circuit. By means of a two-stage summing amplifier in which the second stage (VS2') sums with real factors, while complex factors are implemented in the first stage (VS1'), both balanced- and unbalanced-to-ground interfaces can be implemented in a simple manner with only one capacitance. Common-mode signals are simple to evaluate (SSE); common-mode signalling (DS) is possible.
10	D.-c. summing amplifier drift correction	US40904254	1954-02-09	US2801296A	1957-07-30	BLECHER FRANKLIN H

11	Summing comparator for higher order class D amplifiers	US11389709	2006-03-27	US07498879B2	2009-03-03	Jagadeesh Krishnan; Srinath M. Ramaswamy; Gangadhar Burra
The summing comparator includes: a first integrator; a second integrator for receiving an output of the first integrator; and a comparator for switching when the output of the first integrator is greater than the output of the second integrator. The outputs of the first and second integrators are directly compared by the comparator without the necessity of a summing amplifier.
12	Summing comparator for higher order class D amplifiers	US11389709	2006-03-27	US20070024366A1	2007-02-01	Jagadeesh Krishnan; Srinath Ramaswamy; Gangadhar Burra
The summing comparator includes: a first integrator; a second integrator for receiving an output of the first integrator; and a comparator for switching when the output of the first integrator is greater than the output of the second integrator. The outputs of the first and second integrators are directly compared by the comparator without the necessity of a summing amplifier.
13	Amplificateur sommateur différentiel double à quatre entrées indépendantes	EP87401468.1	1987-06-25	EP0253704A1	1988-01-20	Corpechot, Myriam; Montaron, Joel
Circuit amplificateur et sommateur différentiel double à quatre entrées indépendantes e1, e2, e3, e4, caractérisé en ce qu'il comprend : - deux lignes équipotentielles d'alimentation (L1) et (L2) portées respectivement aux potentiels -V et +V ; - quatre transistors amplificateurs MOS, M1, M2, M3 et M4 dont les grilles constituent les entrées e1, e2, e3, e4, du circuit, les drains D1, D2, D3, D4 desdits transistors étant connectés deux à deux, pour constituer la première sortie du circuit sur laquelle on recueille la tension amplifiée Vs1, et la seconde sortie du circuit sur laquelle on recueille la tension amplifiée Vs2 ; - quatre résistances de charge M5, M6, M7 et M8 reliant respectivement les drains D1, D2, D3, D4 des transistors M1, M2, M3 et M4 à la ligne équipotentielle L1 ; - un transistor MOS, M9 fonctionnant en générateur de courant, dont le drain D9 est relié au point commun aux quatre sources S1, S2, S3, S4 des transistors M1, M2, M3, M4 dont la source S9 est reliée à la ligne équipotentielle L2 et dont la grille g9 est reliée à une source de tension de polarisation Upol3.
14	Summierverstärker mit einem komplexen Gewichtungsfaktor und Schnittstelle mit einem solchen Summierverstärker	EP90122047.5	1990-11-17	EP0436808B1	1995-02-15	Zanzig, Hans-Jürgen

15	Summierverstärker mit einem komplexen Gewichtungsfaktor und Schnittstelle mit einem solchen Summierverstärker	EP90122047.5	1990-11-17	EP0436808A2	1991-07-17	Zanzig, Hans-Jürgen
Bei Summierverstärkern mit rückgekoppelten Operationsverstärkern sind die Gewichtungsfaktoren Quotienten aus dem allen Summanden gemeinsamen Rückkopplungswiderstand und den individuellen Vorwiderständen. Nur der Rückkopplungswiderstand wirkt sich direkt proportional aus. Die individuellen Vorwiderstände wirken umgekehrt proportional. Die Bildung vorgegebener komplexer Gewichtungsfaktoren ist erschwert. Dieser z.B. bei Zweidraht-Vierdraht-Schnittstellen auftretendes Problem wird durch einen Zweistufigen Summierverstärker gelöst, bei dem die zweite Stufe (VS2') mit reellen Faktoren summiert und komplexe Faktoren in der ersten Stufe (VS1') realisiert werden. Dadurch können erdsymmetrische und erdunsymmetrische Schnittstellen gleicherweise einfach mit nur einer Kapazität realisiert werden. Gleichtaktsignale können einfach ausgewertet werden (SSE); eine Gleichtaktsignalisierung (DS) ist möglich.
16	Double differential summing amplifier with four independent inputs	US067592	1987-06-26	US4780630A	1988-10-25	Myriam Corpechot; Joel Montaron
A double differential summing amplifier circuit with four independent inputs, having two equipotential supply lines L1 and L2 raised respectively to potentials -V and +V; four MOS amplifier transistors M1, M2, M3 and M4, the gates of which constitute the inputs e1, e2, e3 and e4 of the circuit and which are respectively connected to sources supplying the voltages to be amplified of values Ve1, Ve2, V33 and Ve4, the drains D1, D2, D3 and D4 of these transistors being connected pairwise, namely D1 and D3 of transistors M1 and M3, on the one hand, for constituting the first output of the circuit on which is collected the amplified voltage Vs1, and D2 and D4 of transistors M2 and M4, on the other hand, for constituting the second output of the circuit on which is collected the amplified voltage Vs2; four load resistors M5, M6, M7 and M8 respectively connecting the drains D1, D2, D3 and D4 of transistors M1, M2, M3 and M4 to equipotential line L1; an MOS transistor M9 functioning as a current generator, whose drain D9 is connected to the common point of the four sources S1, S2, S3 and S4 of transistors M1, M2, M3 and M4, the source S9 of which is connected to equipotential line L2 and whose gate g9 is connected to a polarizing voltage source Upol3.
17	Differential summing amplifier for inputs having large common mode signals	US873228	1986-06-11	US4698599A	1987-10-06	Robert L. Hedman
Differential input voltages are converted into current unbalances in a parallel-branch circuit. A load means converts the sum of the current unbalances to a differential voltage representing the sum of the input voltages.
18	Pure fluid summing impact modulator and universal amplifiers constructed therewith	US42758965	1965-01-25	US3388713A	1968-06-18	GERHARD BJORNSEN BJORN

19	Combination driver-summing circuit for rail-to-rail differential amplifier	US36774	1993-03-25	US5311145A	1994-05-10	Johan H. Huijsing; John P. Tero
A combination driver/summing circuit for rail-to-rail operation of a differential amplifier includes a differential amplifier input stage that amplifies an input signal and a current control circuit that regulates the operating currents through the active elements of the differential amplifier input stage. A summing circuit divided into first and second segments and supplied with current from a single common floating current source combines internal currents supplied by the differential amplifier input stage. A class A-B driver/output stage is coupled to the summing circuit to derive at least one output signal representative of the input signal and which is operative over nearly the full rail-to-rail supply voltage range.
20	Apparatus for stabilizing high-gain direct current transistorized summing amplifier	US1502960	1960-03-11	US3218566A	1965-11-16	HAYES JR MONSON H

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