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REGENERATIVE RELAY CIRCUIT

申请号 JP17973985 申请日 1985-08-14 公开(公告)号 JPS6239909A 公开(公告)日 1987-02-20
申请人 SUMITOMO ELECTRIC INDUSTRIES; 发明人 HIRAOKA SUSUMU; TAKENAKA SHINYA; MATSUOKA HARUJI;
摘要 PURPOSE:To regenerate a reception pulse FM signal whose duty cycle is not 50% due to distortion so as to attain that the duty cycle is 50% by constituting the titled circuit with digital elements only such as a counter, a FIFO memory and a flip-flop. CONSTITUTION:An input signal having a reception waveform whose duty cycle is not 50% and having a period T is counted by a counter 102 for one period and 1/n=(n=1, 2...) of the output is written in the FIFO memory 103. The output of the FIFO memory is inputted to a counter 104, counted down by a clock having a period of n/2 times of the clock of the counter 102 and the state of a flip-flop 104 is changed at every generation of a borrow signal and then an output signal with 50% duty cycle is regenerated from the flip-flop.
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