A withstand voltage structure for a semiconductor device, comprising: a metal layer (107) comprising a high voltage interconnection area (107a) for arranging a high voltage interconnection wire; a dielectric layer (108a), a field oxide layer (108b) and a drift region (102) sequentially located below the high voltage interconnection area (107a); a plurality of semi-insulating resistive field plates (105), each of the semi-insulating resistive field plates (105) being adjacent to the field oxide layer (108b); and a plurality of conductor field plates (106), each of the conductor field plates (106) being located above the semi-insulating resistive field plate (105), and the conductor field plates (106) being in the dielectric layer (108a), wherein the conductor field plates (106) and the semi-insulating resistive field plates (105) constitute a plurality of capacitors, and every two adjacent capacitors share one conductor field plate (106) or semi-insulating resistive field plate (105), such that each capacitor can transfer energy with the other capacitor.