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91. 发明申请

US20170080696A1 METHODS AND APPARATUS FOR TRANSFER FOR FILMS AMONG SUBSTRATES 审中-公开
公开(公告)号：US20170080696A1
公开(公告)日：2017-03-23
申请号：US15219743
申请日：2016-07-26
申请人： GRAPHENE FRONTIERS
发明人： Bruce Ira WILLNER
IPC分类号： B32B37/24 , B32B38/10
CPC分类号： B32B37/24 , B32B38/08 , B32B38/10 , B32B2037/243 , B32B2037/246 , C01B32/184 , C01B32/194 , H01L21/0201 , H01L21/67092 , H01L21/67132
摘要： A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.

92. 发明授权

US09427946B2 Methods and apparatus for transfer of films among substrates 有权
标题翻译：在基片之间转移膜的方法和装置
公开(公告)号：US09427946B2
公开(公告)日：2016-08-30
申请号：US14445746
申请日：2014-07-29
申请人： Graphene Frontiers
发明人： Bruce Ira Willner
IPC分类号： H01L21/02 , H01L21/67 , B32B37/24 , B32B38/08 , C01B31/04
CPC分类号： B32B37/24 , B32B38/08 , B32B38/10 , B32B2037/243 , B32B2037/246 , C01B32/184 , C01B32/194 , H01L21/0201 , H01L21/67092 , H01L21/67132
摘要： A method is disclosed which includes: forming at least one layer of material on at least part of a surface of a first substrate, wherein a first surface of the at least one layer of material is in contact with the first substrate thereby defining an interface; attaching a second substrate to a second surface of the at least one layer of material; forming bubbles at the interface; and applying mechanical force; whereby the second substrate and the at least one layer of material are jointly separated from the first substrate. Related arrangements are also described.
摘要翻译：公开了一种方法，其包括：在第一衬底的表面的至少一部分上形成至少一层材料，其中所述至少一层材料的第一表面与所述第一衬底接触，从而限定界面; 将第二衬底附接到所述至少一层材料的第二表面; 在界面处形成气泡; 并施加机械力; 由此所述第二基板和所述至少一个材料层与所述第一基板共同分离。还描述了相关的布置。

93. 发明授权

US09046545B2 Semiconductor device using a silicon wafer with a pattern arrangement 有权
标题翻译：使用具有图案布置的硅晶片的半导体器件
公开(公告)号：US09046545B2
公开(公告)日：2015-06-02
申请号：US12963862
申请日：2010-12-09
申请人： Tatsuro Takagaki
发明人： Tatsuro Takagaki
IPC分类号： H01L29/06 , H01L21/00 , B65G47/90 , G01P15/08 , H01L41/332 , H01L23/544 , B81C1/00 , G01P15/12 , G01P15/125 , G01P15/18
CPC分类号： H01L27/0207 , B81B2201/0235 , B81B2203/0136 , B81B2207/053 , B81C1/00214 , G01P15/0802 , G01P15/123 , G01P15/125 , G01P15/18 , G01P2015/0814 , G01P2015/0842 , H01L21/0201 , H01L23/544 , H01L41/332 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising: a support part; a flexible part, one end of which is supported by the support part; a spindle part supported by the other end of the flexible part; a displacement detection means which detects displacement of the spindle part; and an aperture part arranged adjacent to the spindle part; wherein a plurality of patterns comprised from the aperture part is formed on a silicon wafer parallel to a first direction and a second direction which intersects the first direction, the plurality of patterns include one or more patterns arranged in a straight line in the first direction and the second direction, the plurality of patterns is arranged so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different.
摘要翻译：一种半导体器件，包括：支撑部分; 柔性部分，其一端由支撑部分支撑; 由所述柔性部件的另一端支撑的主轴部; 检测所述主轴部的位移的位移检测单元; 以及与所述主轴部相邻配置的开口部; 其特征在于，在与所述第一方向相交的第一方向和第二方向平行的硅晶片上形成有从所述开口部构成的多个图案，所述多个图案包括沿所述第一方向排列成直线的一个或多个图案，在第二方向上，多个图案被布置成使得硅晶片的解理面和硅晶片上的图案布置的表面相交的轴与第一方向不同。

94. 发明申请

US20150008454A1 SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20150008454A1
公开(公告)日：2015-01-08
申请号：US14495336
申请日：2014-09-24
申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.
发明人： Keiji ISHIBASHI
IPC分类号： H01L21/304 , H01L21/28 , H01L21/02 , H01L29/16
CPC分类号： H01L21/304 , C30B23/025 , C30B29/36 , C30B33/00 , H01L21/02002 , H01L21/02008 , H01L21/0201 , H01L21/02378 , H01L21/0243 , H01L21/02433 , H01L21/02529 , H01L21/02658 , H01L21/28 , H01L29/045 , H01L29/1608 , H01L29/167 , H01L29/34 , H01L29/36 , H01L29/45 , H01L29/4966 , H01L29/66068 , H01L29/7802 , H01L29/7813 , Y10T428/21
摘要： A substrate capable of achieving a lowered probability of defects produced in a step of forming an epitaxial film or a semiconductor element, a semiconductor device including the substrate, and a method of manufacturing a semiconductor device are provided. A substrate is a substrate having a front surface and a back surface, in which at least a part of the front surface is composed of single crystal silicon carbide, the substrate having an average value of surface roughness Ra at the front surface not greater than 0.5 nm, a standard deviation σ of that surface roughness Ra not greater than 0.2 nm, an average value of surface roughness Ra at the back surface not smaller than 0.3 nm and not greater than 10 nm, standard deviation σ of that surface roughness Ra not greater than 3 nm, and a diameter D of the front surface not smaller than 110 mm.

95. 发明申请

US20140084297A1 GROUP III NITRIDE WAFERS AND FABRICATION METHOD AND TESTING METHOD 审中-公开
标题翻译：第三组氮化物膜和制造方法和测试方法
公开(公告)号：US20140084297A1
公开(公告)日：2014-03-27
申请号：US13798530
申请日：2013-03-13
申请人： Seoul Semiconductor Co., Ltd. , SixPoint Materials, Inc.
发明人： Tadao Hashimoto
IPC分类号： H01L21/66 , H01L29/20 , H01L21/78
CPC分类号： G01N23/207 , B24B37/044 , C01B21/0632 , C01P2002/74 , C30B7/105 , C30B29/403 , C30B29/406 , C30B33/00 , C30B33/06 , H01L21/0201 , H01L21/30625 , H01L21/78 , H01L22/12 , H01L29/045 , H01L29/2003 , H01L2924/0002 , H01L2924/00
摘要： The invention provides, in one instance, a group III nitride wafer sliced from a group III nitride ingot, polished to remove the surface damage layer and tested with x-ray diffraction. The x-ray incident beam is irradiated at an angle less than 15 degree and diffraction peak intensity is evaluated. The group III nitride wafer passing this test has sufficient surface quality for device fabrication. The invention also provides, in one instance, a method of producing group III nitride wafer by slicing a group III nitride ingot, polishing at least one surface of the wafer, and testing the surface quality with x-ray diffraction having an incident beam angle less than 15 degree to the surface. The invention also provides, in an instance, a test method for testing the surface quality of group III nitride wafers using x-ray diffraction having an incident beam angle less than 15 degree to the surface.
摘要翻译：本发明在一个实例中提供了从III族氮化物锭切片的III族氮化物晶片，其被抛光以去除表面损伤层并且用x射线衍射测试。以小于15度的角度照射x射线入射光束，评价衍射峰强度。通过该测试的III族氮化物晶片具有用于器件制造的足够的表面质量。本发明在一个实例中还提供了通过切割III族氮化物锭来抛光晶片的至少一个表面并且用具有入射光束角度较小的x射线衍射测试表面质量来制造III族氮化物晶片的方法比表面15度以上。本发明还提供了一种用于使用具有小于表面15度的入射光束角的x射线衍射来测试III族氮化物晶片的表面质量的测试方法。

96. 发明申请

US20140008768A1 SEMICONDUCTOR WAFER AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体晶圆及其制造方法
公开(公告)号：US20140008768A1
公开(公告)日：2014-01-09
申请号：US14005975
申请日：2012-04-03
申请人： Michito Sato
发明人： Michito Sato
IPC分类号： H01L29/34 , H01L21/02
CPC分类号： H01L29/34 , H01L21/0201 , H01L21/02024
摘要： A semiconductor wafer having sag formed at an outer periphery at the time of polishing, wherein a displacement of the semiconductor wafer in a thickness direction is 100 nm or less between a center and a outer peripheral sag start position of the semiconductor wafer, and the center of the semiconductor wafer has a convex shape, an amount of outer peripheral sag of the semiconductor wafer is 100 nm or less, and the outer peripheral sag start position is away from an outer peripheral portion of the semiconductor wafer toward the center or 20 mm or more away from an outer peripheral end of the semiconductor wafer toward the center, the outer peripheral portion being a measurement target of ESFQR.
摘要翻译：在抛光时在外周形成有凹陷的半导体晶片，其中半导体晶片在厚度方向上的位移在半导体晶片的中心和外周起始位置之间为100nm以下，中心半导体晶片的外周凹陷量为100nm以下，外周凹陷开始位置远离半导体晶片的外周部朝向中心或20mm，或者更远离半导体晶片的外周端朝向中心，外周部是ESFQR的测量对象。

97. 发明申请

US20130285264A1 WAFER ASSEMBLY WITH CARRIER WAFER 有权
标题翻译：带载波的WAFER装配
公开(公告)号：US20130285264A1
公开(公告)日：2013-10-31
申请号：US13539243
申请日：2012-06-29
申请人： I-Hsiung HUANG , Heng-Hsin LIU , Heng-Jen LEE , Chin-Hsiang LIN
发明人： I-Hsiung HUANG , Heng-Hsin LIU , Heng-Jen LEE , Chin-Hsiang LIN
IPC分类号： H01L23/544 , H01L21/02
CPC分类号： H01L21/0201 , H01L21/6835 , H01L2221/6834 , H01L2221/68381
摘要： A wafer assembly includes a process wafer and a carrier wafer. Integrated circuits are formed on the process wafer. The carrier wafer is bonded to the process wafer. The carrier wafer has at least one alignment mark.
摘要翻译：晶片组件包括处理晶片和载体晶片。集成电路形成在处理晶片上。载体晶片结合到工艺晶片。载体晶片具有至少一个对准标记。

98. 发明申请

US20130269368A1 THERMAL PLATE WITH PLANAR THERMAL ZONES FOR SEMICONDUCTOR PROCESSING 有权
标题翻译：具有用于半导体加工的平面热区的热板
公开(公告)号：US20130269368A1
公开(公告)日：2013-10-17
申请号：US13912907
申请日：2013-06-07
申请人： Lam Research Corporation
发明人： Keith William GAFF , Keith Comendant , Anthony Ricci
IPC分类号： F25B21/04 , H01L35/34 , H01L21/02
CPC分类号： F25B21/04 , H01L21/0201 , H01L21/67109 , H01L21/67248 , H01L21/6831 , H01L35/34 , Y10T29/49083 , Y10T29/49165
摘要： A thermal plate for a substrate support assembly in a semiconductor plasma processing apparatus, includes multiple independently controllable planar thermal zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones. Each planar thermal zone uses at least one Peltier device as a thermoelectric element. A substrate support assembly in which the thermal plate is incorporated has an electrostatic clamping electrode layer and a temperature controlled base plate. Methods for manufacturing the thermal plate include bonding together ceramic or polymer sheets having planar thermal zones, positive, negative and common lines and vias.
摘要翻译：在半导体等离子体处理装置中用于衬底支撑组件的热板包括以可伸缩复用布局布置的多个可独立控制的平面热区，以及用于独立地控制和供电平面加热器区的电子装置。每个平面热区使用至少一个珀耳帖装置作为热电元件。其中结合有热敏板的基板支撑组件具有静电夹持电极层和温度控制的基板。用于制造热板的方法包括将具有平面热区域，正，负和公共线路和通孔的陶瓷或聚合物片材结合在一起。

99. 发明申请

US20130244405A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130244405A1
公开(公告)日：2013-09-19
申请号：US13747046
申请日：2013-01-22
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Masanori Terahara , Hikaru Kokura , Akihiro Hasegawa , Atsuo Fushida , Fumihiko Akaboshi
IPC分类号： H01L21/02
CPC分类号： H01L21/0201 , H01J37/321 , H01L21/32137 , H01L21/67103 , H01L21/67109 , H01L21/6831
摘要： A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating.
摘要翻译：制造本文公开的半导体器件的方法包括：将衬底安装在放置在室内的静电吸盘上，所述静电吸盘具有第一温度，并且所述衬底预先保持在具有低于第一温度的第二温度的气氛中; 通过向静电卡盘施加电压将基板固定到静电卡盘上; 在安装基板之后，将静电卡盘加热至高于第一温度和第二温度的第三温度; 并在加热之后处理基板。

100. 发明申请

US20130152852A1 LARGE ALUMINUM NITRIDE CRYSTALS WITH REDUCED DEFECTS AND METHODS OF MAKING THEM 有权
标题翻译：具有减少缺陷的大型氮化铝晶体及其制备方法
公开(公告)号：US20130152852A1
公开(公告)日：2013-06-20
申请号：US13706966
申请日：2012-12-06
申请人： Crystal IS, Inc.
发明人： Robert T. Bondokov , Kenneth E. Morgan , Glen A. Slack , Leo Schowalter
IPC分类号： C30B25/02 , B28D5/00
CPC分类号： C30B33/02 , B28D5/00 , C23C16/34 , C30B23/00 , C30B23/02 , C30B25/02 , C30B25/08 , C30B25/10 , C30B25/18 , C30B29/403 , H01L21/0201 , H01L21/02389 , H01L21/0254 , H01L21/30625 , Y10T428/21
摘要： Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm−2 and an inclusion density below 104 cm−3 and/or a MV density below 104 cm−3.
摘要翻译：降低AlN中的微孔（MV）密度改善了与晶体生长期间的开裂有关的许多问题，抛光期间的蚀刻坑产生，AlN晶片中的光学透明度的降低以及可能的AlN的外延生长期间的生长凹坑形成和/ 或AlGaN。这有助于实际的晶体生产策略和形成具有低缺陷密度（例如，位错密度低于104cm -2）和包含密度低于104cm -3和/或低于104cm -3的MV密度的大体积AlN晶体。

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