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91. 发明公开

EP1709686A2 APPARATUS INCORPORATING SMALL-FEATURE-SIZE AND LARGE-FEATURE-SIZE COMPONENTS AND METHOD FOR MAKING SAME 审中-公开
标题翻译：与用于生产小尺寸的结构元素和巨大的结构元素尺寸和流程组件设备
公开(公告)号：EP1709686A2
公开(公告)日：2006-10-11
申请号：EP05726384.0
申请日：2005-01-28
申请人： Alien Technology Corporation
发明人： SWINDLEHURST, Susan , HADLEY, Mark, A. , DRZAIC, Paul, S. , CRAIG, Gordon, S., W. , GENGEL, Glenn , HERRMANN, Scott , TOOTOOCHI, Aly , EISENHARDT, Randolph, W.
IPC分类号： H01L25/16 , H01L23/498 , H01L23/538 , H01L21/60
CPC分类号： G06K19/07752 , G06K19/077 , H01L23/49855 , H01L23/5389 , H01L24/13 , H01L24/19 , H01L24/24 , H01L24/29 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/90 , H01L24/95 , H01L24/97 , H01L29/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/13019 , H01L2224/13099 , H01L2224/1319 , H01L2224/13499 , H01L2224/16225 , H01L2224/16227 , H01L2224/24011 , H01L2224/2402 , H01L2224/24137 , H01L2224/24225 , H01L2224/24227 , H01L2224/29101 , H01L2224/2929 , H01L2224/293 , H01L2224/29339 , H01L2224/73104 , H01L2224/73204 , H01L2224/76155 , H01L2224/81201 , H01L2224/81205 , H01L2224/81207 , H01L2224/81224 , H01L2224/81801 , H01L2224/81898 , H01L2224/81903 , H01L2224/82102 , H01L2224/83191 , H01L2224/83192 , H01L2224/838 , H01L2224/83865 , H01L2224/83868 , H01L2224/83871 , H01L2224/83874 , H01L2224/95085 , H01L2224/95136 , H01L2224/97 , H01L2924/00013 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/0781 , H01L2924/10158 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15155 , H01L2924/15165 , H01L2924/3011 , H01L2224/82 , H01L2924/00 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2924/00012 , H01L2224/05599
摘要： An apparatus incorporating small-feature size and large-feature-size components. The apparatus comprise a strap including a substrate with an integrated circuit contained therein. The integrated circuit coupling to a first conductor disposed on the substrate. The first conductor is made of a thermosetting or a thermoplastic material including conductive fillers. A large-scale component having a second conductor is electrically coupled to the first conductor to electrically couple the large-scale component to the integrated circuit. The large-scale component includes a second substrate.

92. 发明公开

EP3391415A1 SUPERCONDUCTING BUMP BONDS 有权
公开(公告)号：EP3391415A1
公开(公告)日：2018-10-24
申请号：EP15828622.9
申请日：2015-12-30
申请人： Google LLC , Mutus, Joshua Yousouf , Lucero, Erik Anthony
发明人： MUTUS, Joshua Yousouf , LUCERO, Erik Anthony
IPC分类号： H01L27/18 , H01L23/498
CPC分类号： H01L39/045 , H01L23/49816 , H01L23/49888 , H01L24/03 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L27/18 , H01L2224/0345 , H01L2224/0362 , H01L2224/0381 , H01L2224/03826 , H01L2224/0384 , H01L2224/0401 , H01L2224/05023 , H01L2224/05025 , H01L2224/05124 , H01L2224/05179 , H01L2224/05186 , H01L2224/05564 , H01L2224/05568 , H01L2224/05669 , H01L2224/05684 , H01L2224/05686 , H01L2224/1145 , H01L2224/1181 , H01L2224/13023 , H01L2224/13109 , H01L2224/13116 , H01L2224/13164 , H01L2224/13179 , H01L2224/13183 , H01L2224/16145 , H01L2224/81013 , H01L2224/81193 , H01L2224/81201 , H01L2224/81409 , H01L2225/06513 , H01L2225/06541 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/20102 , H01L2924/00014 , H01L2924/04941
摘要： A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

93. 发明公开

EP3355342A1 LASER ASSISTED SOLDER BONDING OF DIRECT CONVERSION COMPOUND SEMICONDUCTOR DETECTOR 审中-公开
公开(公告)号：EP3355342A1
公开(公告)日：2018-08-01
申请号：EP17153476.1
申请日：2017-01-27
申请人： Detection Technology Oy
发明人： Heikkinen, Petteri , Johansson, Mikael
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L24/11 , H01L24/92 , H01L27/14636 , H01L27/14661 , H01L27/1469 , H01L31/0256 , H01L2224/0401 , H01L2224/05569 , H01L2224/11312 , H01L2224/11318 , H01L2224/131 , H01L2224/13111 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/16227 , H01L2224/81191 , H01L2224/81192 , H01L2224/81201 , H01L2224/81224 , H01L2224/81815 , H01L2224/81986 , H01L2224/9202 , H01L2924/014 , H01L2224/11 , H01L2924/01082 , H01L2924/00014
摘要： In an embodiment, a method comprises: configuring a direct conversion compound semiconductor sensor over a first surface of a readout integrated circuit, IC, comprising two surfaces, each surface comprising solder material on the surface; illuminating the solder material with an infra-red laser such that the solder material on the readout IC melts and forms solder joints between the readout IC and the direct conversion compound semiconductor sensor; configuring a substrate over a second surface of the readout IC comprising solder material; and illuminating the solder material of the second surface with the infra-red laser such that the solder material on the readout IC melts and electrically connects the readout IC with the substrate. In other embodiments, a high frequency radiation detector and an imaging apparatus are discussed.

94. 发明公开

EP2923999A2 DIE INTERCONNECT 审中-公开
标题翻译： CHIPVERBINDUNGSSTRUKTUR
公开(公告)号：EP2923999A2
公开(公告)日：2015-09-30
申请号：EP15159573.3
申请日：2015-03-18
申请人： NXP B.V.
发明人： van Gemert, Leonardus , Tak, Coenraad , Oldsen, Marten , Bouman, Hendrik
IPC分类号： B81B7/00
CPC分类号： H01L24/17 , B81B7/0048 , B81B7/007 , H01L24/11 , H01L24/14 , H01L24/73 , H01L2224/10135 , H01L2224/10165 , H01L2224/131 , H01L2224/1329 , H01L2224/13339 , H01L2224/1401 , H01L2224/14134 , H01L2224/16238 , H01L2224/1701 , H01L2224/26165 , H01L2224/26175 , H01L2224/29013 , H01L2224/29035 , H01L2224/32225 , H01L2224/73103 , H01L2224/73203 , H01L2224/73204 , H01L2224/81201 , H01L2224/81801 , H01L2224/81855 , H01L2224/83855 , H01L2224/92125 , H01L2924/35 , H01L2924/351 , H01L2924/00014 , H01L2924/00012 , H01L2924/014
摘要： One example embodiment discloses a chip having a chip area, wherein the chip area includes: an overhang area; a rigid coupling area, having a set of rigid coupling points, located on one side of the overhang area; and a flexible coupling area, having a set of flexible coupling points, located on a side of the overhang area opposite to the a rigid coupling area. Another example embodiment discloses a method for fabricating a die interconnect, comprising:
fabricating a rigid coupler area, having a set of rigid coupler points, within a chip having a chip area; defining an overhang area within the chip area and abutted to the rigid coupler area; and
fabricating a flexible coupler area, having a set of flexible coupler points, within the chip area abutted to a side of the overhang area opposite to the rigid coupler area.
摘要翻译：一个示例性实施例公开了一种具有芯片面积的芯片，其中芯片区域包括：突出区域; 刚性联接区域，具有位于所述伸出区域的一侧上的一组刚性联接点; 以及柔性联接区域，其具有一组柔性联接点，位于与刚性联接区域相对的伸出区域的一侧。另一示例性实施例公开了一种用于制造管芯互连的方法，包括：在具有芯片面积的芯片内制造具有一组刚性耦合点的刚性耦合器区域; 限定所述芯片区域内的悬垂区域并与所述刚性耦合器区域相邻; 以及在与所述刚性联接器区域相对的所述伸出区域的一侧的所述芯片区域内制造具有一组柔性耦合点的柔性耦合器区域。

95. 发明公开

EP2836966A1 TRANSPONDERLAGE UND VERFAHREN ZU DEREN HERSTELLUNG 有权
公开(公告)号：EP2836966A1
公开(公告)日：2015-02-18
申请号：EP13717708.5
申请日：2013-04-04
申请人： Smartrac IP B.V.
发明人： KUSCHEWSKI, Martin , RIETZLER, Manfred
IPC分类号： G06K19/077
CPC分类号： G06K19/07754 , G06K19/07722 , G06K19/0775 , H01L24/81 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81201 , H01L2224/81224 , H01L2224/8185 , H01L2924/12042 , H01L2924/141 , H01L2924/00
摘要： The invention relates to a transponder layer (10), in particular for producing a chip card, comprising an antenna substrate (12), on an antenna side (11) of which an antenna (14) made of a wire conductor (13) is provided and which has a chip receiving area formed by a recess in the antenna substrate, wherein a chip (21) is received in said chip receiving area. Wire conductor ends which are used to form terminal ends (15) of the antenna are formed on a chip receiving area base (20) which is set back relative to the rear face (26) of the antenna substrate (12). The chip is received in the chip receiving area such that terminal contacts (22) arranged on a contact face (36) of the chip are contacted with flat contact areas (19) of the terminal ends (15), and the chip semiconductor body (28) rear face (27) which lies opposite the terminal contacts are substantially flush with the rear face of the antenna substrate. The invention further relates to a method for producing a transponder layer.
摘要翻译：本发明涉及一种尤其用于制造芯片卡的应答器层（10），该应答器层在天线侧（11）上包括天线基板（12），天线侧（11）中由导线（13）制成的天线（14）并且其具有由天线衬底中的凹槽形成的芯片容纳区域，其中芯片（21）容纳在所述芯片容纳区域中。用于形成天线的终端（15）的导线端部形成在相对于天线基板（12）的后表面（26）后退的芯片接收区域基座（20）上。芯片容纳在芯片容纳区域中，使得布置在芯片的接触面（36）上的端子触点（22）与端子端部（15）的平坦接触区域（19）接触，并且芯片半导体主体 28）与终端触点相对的后表面（27）基本上与天线基板的后表面齐平。本发明还涉及一种用于制造应答器层的方法。

96. 发明公开

EP2693468A1 Procédé d'assemblage de deux composants électroniques entre eux, de type flip-chip 有权
标题翻译：维尔法罕zum Zusammenbauen zweier elektronischer Bauteile，呕吐类型Flip-Chip-Kontakt
公开(公告)号：EP2693468A1
公开(公告)日：2014-02-05
申请号：EP13178410.0
申请日：2013-07-29
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
发明人： Goubault de Brugiere, Baptiste , Bedoin, Alexis
IPC分类号： H01L23/00
CPC分类号： H01L24/81 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/83 , H01L24/92 , H01L2224/13005 , H01L2224/13082 , H01L2224/13109 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13147 , H01L2224/1403 , H01L2224/14051 , H01L2224/14131 , H01L2224/1416 , H01L2224/14505 , H01L2224/1601 , H01L2224/16104 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17505 , H01L2224/73103 , H01L2224/73203 , H01L2224/81099 , H01L2224/8114 , H01L2224/81193 , H01L2224/81201 , H01L2224/81345 , H01L2224/8183 , H01L2224/83102 , H01L2224/9221 , H01L2924/0132 , H01L2924/0133 , H01L2924/00014 , H01L2924/01047 , H01L2924/0105 , H01L2924/0001 , H01L2924/01029 , H01L2924/01049 , H01L2224/81 , H01L2224/83 , H01L2924/00011
摘要： L'invention concerne un procédé d'assemblage de type flip-chip, de deux composants microélectroniques (1, 2) l'un à l'autre.
Selon l'invention, on prévoit soit de dimensionner des cales (24) en sus des protubérances d'interconnexion (22) soit de sur-dimensionner ces dernières de sorte que leur déformation revienne élastique une fois le contact d'assemblage entre composants (1, 2) atteint, après avoir été plastique lors de l'insertion par des inserts (12) de connexion.
Grâce à l'invention, on peut maîtriser très finement l'espacement entre les deux composants lors de leur assemblage et ceci sans ajouter d'étape supplémentaire à leur fabrication ni au process d'assemblage.
摘要翻译：该方法包括对准互连突起（22）的导体插入件（12）。确定楔（24）的高度（H），使得当组件组装时，高度大于插入件的高度。确定楔的接触表面，使得突起中产生的应力产生的应力等于突起和表面的接触表面的力和加法的比例小于或等于弹性极限。施加恒定力以穿透突起中的插入件，直到在楔块之间获得组装接触。

97. 发明公开

EP1913631A4 3D IC METHOD AND DEVICE 审中-公开
标题翻译： 3D IC的方法和装置
公开(公告)号：EP1913631A4
公开(公告)日：2011-10-05
申请号：EP06789507
申请日：2006-08-07
申请人： ZIPTRONIX INC
发明人： ENQUIST PAUL M , FOUNTAIN GAIUS GILLMAN JR , TONG QIN-YI
IPC分类号： H01L25/065 , H01L21/60 , H01L21/768 , H01L21/98 , H01L23/48
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/81121 , H01L2224/81201 , H01L2224/8123 , H01L2224/81801 , H01L2224/81894 , H01L2224/81931 , H01L2224/83894 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2224/81
摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure (12, 82) is bonded to a second element having a second contact structure (17, 87). First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via (50, 55) may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.; Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

98. 发明公开

EP1775768A1 SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STACK STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译： HALBLEITERBAUELEMENT MIT DREIDIMENSIONALER STAPELSTRUKTUR UND HERSTELLUNGSVERFAHRENDAFÜR
公开(公告)号：EP1775768A1
公开(公告)日：2007-04-18
申请号：EP05751423.4
申请日：2005-06-03
申请人： ZyCube Co., Ltd.
发明人： KOYANAGI, Mitsumasa
IPC分类号： H01L25/065 , H01L21/60 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L23/295 , H01L23/3135 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/20 , H01L24/24 , H01L24/73 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/95 , H01L24/96 , H01L25/0657 , H01L25/50 , H01L2224/10135 , H01L2224/10165 , H01L2224/12105 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13184 , H01L2224/13609 , H01L2224/13644 , H01L2224/1403 , H01L2224/14131 , H01L2224/14505 , H01L2224/14515 , H01L2224/1703 , H01L2224/17505 , H01L2224/17515 , H01L2224/29111 , H01L2224/2919 , H01L2224/33181 , H01L2224/73104 , H01L2224/73253 , H01L2224/73259 , H01L2224/81097 , H01L2224/8114 , H01L2224/81191 , H01L2224/81193 , H01L2224/81194 , H01L2224/81201 , H01L2224/8121 , H01L2224/81815 , H01L2224/81895 , H01L2224/83007 , H01L2224/83101 , H01L2224/83193 , H01L2224/83825 , H01L2224/83862 , H01L2224/83874 , H01L2224/92125 , H01L2224/92133 , H01L2224/92135 , H01L2224/92224 , H01L2224/92244 , H01L2224/97 , H01L2225/06513 , H01L2225/06582 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01057 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/12043 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/3511 , H01L2224/81 , H01L2924/00014 , H01L2224/82 , H01L2224/45111 , H01L2924/01014 , H01L2224/13099 , H01L2924/00
摘要： A three-dimensional stacked structured semiconductor device comprising semiconductor circuit layers stacked on a support substrate, and a method of fabricating the device are provided.
After fixing semiconductor chips 37 to a support substrate 31 with bump electrodes, gaps between the chips 37 are filled with an electrically insulative adhesive 38. Then, by polishing the reverses of the chips 37, the chips 37 are thinned to expose buried interconnections in the chips 37, thereby forming a first semiconductor circuit layer L1. Next, after fixing semiconductor chips 43 to the first semiconductor circuit layer L1 with bump electrodes 41 and 42 by way of an insulating layer 39, gaps between the chips 43 are filled with an electrically insulative adhesive 44. Then, by polishing the reverses of the chips 43, the chips 43 are thinned to expose buried interconnections in the chips 43, thereby forming a second semiconductor circuit layer L2. In a similar way, semiconductor chips 49 are fixed to the second semiconductor circuit layer L2 by way of an insulating layer 45, thereby forming a third semiconductor circuit layer L3. Dicing is performed as necessary. Thus, three-layer stacked structured semiconductor devices 30A, 30B, and 30C are obtained.
摘要翻译：提供了包括堆叠在支撑衬底上的半导体电路层的三维堆叠结构的半导体器件，以及制造该器件的方法。在将半导体芯片37固定到具有凸起电极的支撑基板31上之后，用电绝缘粘合剂38填充芯片37之间的间隙。然后，通过抛光芯片37的反向，使芯片37变薄以暴露出掩埋的互连芯片37，从而形成第一半导体电路层L1。接下来，在通过绝缘层39将半导体芯片43固定到具有凸块电极41和42的第一半导体电路层L1之后，用电绝缘粘合剂44填充芯片43之间的间隙。然后，通过抛光芯片43，芯片43变薄以暴露芯片43中的掩埋互连，从而形成第二半导体电路层L2。以类似的方式，半导体芯片49通过绝缘层45固定到第二半导体电路层L2，从而形成第三半导体电路层L3。必要时进行切割。因此，获得三层堆叠结构的半导体器件30A，30B和30C。

99. 发明公开

EP1714319A2 SEMICONDUCTOR CHIP PACKAGE 审中-公开
标题翻译：半导体芯片包封
公开(公告)号：EP1714319A2
公开(公告)日：2006-10-25
申请号：EP04815317.5
申请日：2004-12-21
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： ARNOLD, Richard, Willson , COWENS, Marvin, Wayne , ODEGARD, Charles, Anthony
IPC分类号： H01L23/48
CPC分类号： H01L24/16 , H01L21/563 , H01L23/49822 , H01L24/11 , H01L24/12 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/05568 , H01L2224/05573 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05684 , H01L2224/10135 , H01L2224/1134 , H01L2224/13099 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16237 , H01L2224/73203 , H01L2224/73204 , H01L2224/81136 , H01L2224/8114 , H01L2224/81141 , H01L2224/81201 , H01L2224/81801 , H01L2224/838 , H01L2924/01004 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01061 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/0781 , H01L2924/14 , H01L2924/15311 , H01L2924/16152 , H01L2924/351 , H01L2924/00 , H01L2924/00014
摘要： A semiconductor chip package includes an integrated circuit chip (22) and a substrate (24). A chip contact pad (42) is formed on a first side (44) of the chip (22). A stud (46) is formed on the chip contact pad (42) from wire using a wire bonding machine. The stud (46) has a partially squashed ball portion (47) bonded to the chip contact pad (42). The stud (46) also has an elongated portion extending from the partially squashed ball portion. A first layer (48) of insulating material is on a first side (50) of the substrate (24). A bottomed well (54) is formed in the first layer (48) and opens to the first side (50) of the substrate (24). A first conductive material (60) at least partially fills the well (54). The first conductive material (60) is electrically connected to at least one trace line (64) in the substrate (24). The stud (46) is partially embedded in the first conductive material (60) to form an electrical connection between the chip (22) and the substrate (24).

100. 发明公开

EP3195357A4 METHODS TO FORM HIGH DENSITY THROUGH-MOLD INTERCONNECTIONS 审中-公开
公开(公告)号：EP3195357A4
公开(公告)日：2018-05-23
申请号：EP14901926
申请日：2014-09-15
申请人： INTEL CORP
发明人： KARHADE OMKAR G , DESHPANDE NITIN A , CETEGEN EDVIN , LI ERIC J , MALLIK DEBENDRA , ZIADEH BASSAM M
IPC分类号： H01L25/065 , H01L23/48
CPC分类号： H01L25/0657 , H01L21/565 , H01L21/76802 , H01L21/76877 , H01L23/3142 , H01L23/49811 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/1329 , H01L2224/133 , H01L2224/16227 , H01L2224/16235 , H01L2224/32225 , H01L2224/73204 , H01L2224/81201 , H01L2224/81203 , H01L2224/81205 , H01L2224/81207 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2225/06517 , H01L2225/06548 , H01L2225/1023 , H01L2225/1058 , H01L2924/01028 , H01L2924/01047 , H01L2924/01079 , H01L2924/01322 , H01L2924/0133 , H01L2924/014 , H01L2924/1433 , H01L2924/1434 , H01L2924/15192 , H01L2924/15311 , H01L2924/1579 , H01L2924/1815 , H01L2924/01082 , H01L2924/0105 , H01L2924/00012 , H01L2924/01083 , H01L2924/01029 , H01L2924/00014 , H01L2924/0665
摘要： Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads and at least one interconnection bond pad formed in and/or on an active surface thereof, attaching a microelectronic device to the plurality of microelectronic device attachment bond pads, forming a mold chase having a mold body and at least one projection extending from the mold body, wherein the at least one projection includes at least one sidewall and a contact surface, contacting the mold chase projection contact surface to a respective microelectronic substrate interconnection bond pad, disposing a mold material between the microelectronic substrate and the mold chase, and removing the mold chase to form at least one interconnection via extending from a top surface of the mold material to a respective microelectronic substrate interconnection bond pad.

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