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21. 发明授权

US6107183A Method of forming an interlevel dielectric 失效
标题翻译：形成层间电介质的方法
公开(公告)号：US6107183A
公开(公告)日：2000-08-22
申请号：US677514
申请日：1996-07-10
申请人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
发明人： Gurtej Sandhu , Anand Srinivasan , Ravi Iyer
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76837
摘要： An interlevel dielectric structure includes forming first and second dielectric layers between which are located lines of a conductive material that are also formed with a dielectric material in spaces between the lines of conductive material, with the lower surface of the dielectric material extending lower than the lower surface of lines of conductive material adjacent thereto, and the upper surface of the dielectric material extending higher than the upper surface of conductive material adjacent thereto, thus reducing fringe and total capacitance between the lines of conductive material. The dielectric material, which has a dielectric constant of less than about 3.6, does not extend directly above the upper surface of the lines of conductive material, allowing formation of subsequent contacts down to the lines of conductive material without exposing the dielectric material to further processing. Various methods for forming the interlevel dielectric structure are disclosed.
摘要翻译：层间电介质结构包括形成第一和第二电介质层，它们之间位于导电材料的定位线之间，导电材料的导电材料线之间的空间中还形成介电材料，电介质材料的下表面延伸低于下部电介质材料与其相邻的导电材料的线的表面，并且电介质材料的上表面比与其相邻的导电材料的上表面延伸，从而减少导电材料线之间的条纹和总电容。具有小于约3.6的介电常数的电介质材料不直接在导电材料线的上表面的上方延伸，从而允许随后的触点形成至导电材料的线，而不会将电介质材料暴露于进一步的加工。公开了形成层间电介质结构的各种方法。

22. 发明授权

US6091150A Integrated circuitry comprising electrically insulative material over interconnect line tops, sidewalls and bottoms 有权
标题翻译：集成电路，包括互连线顶部，侧壁和底部上的电绝缘材料
公开(公告)号：US6091150A
公开(公告)日：2000-07-18
申请号：US272060
申请日：1999-03-18
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76838 , H01L23/5222 , H01L2924/0002
摘要： A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the interconnect line over the etched second insulating material. The method further comprises provision of a base electrically conductive layer beneath the first insulating material, with the anisotropically etching step etching through the first insulating material to the base conductive layer, and the conductive layer being provided in electrical connection with the base conductive layer. Integrated circuitry produced by the method and other methods is also disclosed.
摘要翻译：一种形成具有与其主要共同延伸的导电覆盖层的导电互连线的半导体处理方法包括：a）在第一电绝缘材料上提供导电互连线，该线具有顶部和侧壁; b）在所述互连线和所述第一绝缘材料上选择性地沉积第二电绝缘材料层，所述第二电绝缘材料层以在所述互连线上方沉积更大厚度的所述第二绝缘材料的厚度大于所述第一绝缘材料上所述第二绝缘材料的厚度; c）将第二绝缘材料层向内各向异性地蚀刻至少至少第一绝缘材料，同时将第二绝缘材料留在互连线的顶部和侧壁上; 以及d）在各向异性蚀刻的第二绝缘层上方设置导电层，以形成导电层，该导电层与蚀刻的第二绝缘材料上的互连线主要共同延伸。该方法还包括在第一绝缘材料下面提供基底导电层，各向异性蚀刻步骤通过第一绝缘材料蚀刻到基底导电层，并且导电层设置为与基底导电层电连接。还公开了通过该方法和其它方法生产的集成电路。

23. 发明授权

US6046098A Process of forming metal silicide interconnects 失效
标题翻译：形成金属硅化物互连的工艺
公开(公告)号：US6046098A
公开(公告)日：2000-04-04
申请号：US27603
申请日：1998-02-23
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/337 , H01L21/4763
CPC分类号： H01L29/66606 , H01L21/28052 , H01L21/32051
摘要： A process for forming a metal suicide interconnect includes applying a layer of polysilicon over a semiconductor layer. A layer of amorphous silicon is formed over the layer of polysilicon followed by a layer of metal, such as titanium, over the layer of amorphous silicon. The layer of titanium is reacted with the layer of amorphous silicon to form a small grain C49 layer of titanium silicide. The layer of polysilicon and the layer of titanium silicide are etched to form a desired interconnect structure. The small grain C49 layer of titanium silicide is then converted to the C54 phase.
摘要翻译：形成金属硅化物互连的方法包括在半导体层上施加多晶硅层。在多晶硅层之后形成非晶硅层，然后在非晶硅层上形成一层金属，例如钛。钛层与非晶硅层反应形成小的C49硅化钛层。蚀刻多晶硅层和硅化钛层以形成所需的互连结构。然后将小粒C49硅化钛层转化为C54相。

24. 发明授权

US5946542A Method of depositing passivation layers on semiconductor device arrays 失效
标题翻译：在半导体器件阵列上沉积钝化层的方法
公开(公告)号：US5946542A
公开(公告)日：1999-08-31
申请号：US605524
申请日：1996-02-26
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C23C16/30 , H01L21/314 , H01L21/56 , H01L21/316
CPC分类号： C23C16/308 , H01L21/3145 , H01L21/56 , H01L2924/0002
摘要： A method of forming a silicon oxynitride (SiO.sub.x N.sub.y) passivation layer on a first side of a silicon wafer that has a plurality of parallel spaced conductive runners positioned thereon. The method comprises the steps of mixing TEOS, Oxygen, Nitrogen and either Ammonia or Diethyl amine and then introducing the mixture into a plasma deposition chamber containing the wafers that are to receive the passivation layer. The mixture is then energized into a plasma which results in a silicon oxynitride passivation layer being deposited onto the upper surface of the silicon wafer. Due to the characteristics of the TEOS gas, the passivation layer is very conformal which reduces the formation of keyholes in the passivation layer.
摘要翻译：在硅晶片的第一面上形成氮氧化硅（SiO x N y）钝化层的方法，该硅晶片的第一面上具有多个平行间隔开的导电流道。该方法包括以下步骤：将TEOS，氧气，氮气和氨或二乙胺混合，然后将混合物引入含有待接收钝化层的晶片的等离子体沉积室中。然后将混合物通电为等离子体，这导致硅氧化硅钝化层沉积在硅晶片的上表面上。由于TEOS气体的特性，钝化层是非常共形的，这减少了钝化层中键孔的形成。

25. 发明授权

US5872052A Planarization using plasma oxidized amorphous silicon 失效
标题翻译：使用等离子体氧化非晶硅的平面化
公开(公告)号：US5872052A
公开(公告)日：1999-02-16
申请号：US599675
申请日：1996-02-12
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/321
CPC分类号： H01L21/02238 , H01L21/02252 , H01L21/3105 , H01L21/31051 , H01L21/316 , H01L21/31662 , H01L21/32105
摘要： A planarization process for filling spaces between patterned metal features formed over a surface of a semiconductor substrate. The patterned metal features are preferably coated with a dielectric barrier. The dielectric barrier is coated with an material that expands during oxidation or nitridization to a thickness about half the depth of the space between metallized features. The layer is then plasma oxidized using an RF or ECR plasma at low temperature with an oxygen ambient. Alternatively, the layer is plasma nitridized at low temperature. The plasma oxidation or nitridization is continued until the expandable material is converted to a dielectric and has expanded to fill the space between patterned metal features. Optionally, the process can be followed by a mechanical or chemical mechanical planarization step.
摘要翻译：用于填充在半导体衬底的表面上形成的图案化金属特征之间的空间的平坦化处理。图案化的金属特征优选地涂覆有电介质阻挡层。电介质阻挡层涂覆有在氧化或氮化期间膨胀至金属化特征之间的空间深度的大约一半厚度的材料。然后使用RF或ECR等离子体在低温和氧气氛下对该层进行等离子体氧化。或者，该层在低温下被等离子体氮化。等离子体氧化或氮化继续直到可膨胀材料转化为电介质并且已经膨胀以填充图案化的金属特征之间的空间。任选地，该过程可以之后是机械或化学机械平面化步骤。

26. 发明授权

US5817175A Method of reducing carbon incorporation into films produced by chemical vapor deposition involving organometallic precursor compounds 失效
公开(公告)号：US5817175A
公开(公告)日：1998-10-06
申请号：US506535
申请日：1995-07-25
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： C23C16/18 , C23C16/34 , C23C16/452 , C30B25/10 , C30B25/02
CPC分类号： C30B25/105 , C23C16/18 , C23C16/34 , C23C16/452 , C30B29/02
摘要： A semiconductor processing method of depositing a film on a substrate using an organometallic precursor, where the precursor comprises a coordination complex having a central linking atom and at least two ligands bonded thereto, at least one of the ligands including an organic species comprising a carbon atom having at least one hydrogen atom bonded thereto thereby defining a carbon-hydrogen bond of the species, includes, a) passing a feed material through a plasma generating location effective to induce the feed material into a plasma state; b) flowing the feed material from the plasma generating location, the feed material flowing from the plasma generating location comprising a gas in an activated metastable state; c) combining an organometallic precursor with the gas when the gas is in the activated metastable state to separate the organic species from the organometallic precursor coordination complex while leaving the carbon-hydrogen bond intact, the organometallic precursor being in a gaseous non-plasma state when combined with the activated metastable state gas; and d) passing the combined precursor and gas to a substrate under conditions effective to deposit a film on the substrate, the film comprising the central linking atom.

27. 发明授权

US5736455A Method for passivating the sidewalls of a tungsten word line 失效
标题翻译：钝化钨字线侧壁的方法
公开(公告)号：US5736455A
公开(公告)日：1998-04-07
申请号：US577856
申请日：1995-12-22
申请人： Ravi Iyer , Pai Hung Pan
发明人： Ravi Iyer , Pai Hung Pan
IPC分类号： H01L21/28 , H01L21/768 , H01L21/283 , H01L21/336
CPC分类号： H01L21/76889 , H01L21/28061
摘要： This invention embodies a process for passivating the edges of a tungsten metal layer within a word line stack. After the word line stack is patterned (i.e., formed by masking and etching the stack of globally-deposited layers) as shown in FIG. 1, a conformal silicon film is blanket deposited. Deposition of the silicon film may be accomplished by any available technique, such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. The wafer is then heated so that the tungsten in contact with the silicon film is converted to tungsten silicide. In a preferred embodiment of the invention, only a portion of the silicon film is allowed to react with the edge of the tungsten layer. The remainder of the silicon film is converted to silicon dioxide by subjecting the wafer O.sub.2 in a furnace or rapid thermal processing chamber. Alternatively, the remainder of the silicon film may be converted to silicon dioxide by subjecting the wafer to O.sub.2 or O.sub.3 in a plasma reactor. In an alternative but equivalent embodiment of the process, the tungsten metal is converted to tungsten silicide and the remainder of the silicon film is converted to silicon dioxide using a single piece of equipment. This is done by first heating the wafer in a nitrogen-containing ambiance, and then ramping the temperature upward and replacing the nitrogen-containing ambiance with an oxidizing ambiance.
摘要翻译：本发明体现了一种用于钝化字线堆叠内的钨金属层的边缘的方法。在字线堆叠被图案化之后（即，通过掩模和蚀刻全局沉积层的堆叠形成），如图1所示。如图1所示，保形硅膜被覆盖。硅膜的沉积可以通过任何可用的技术来实现，例如化学气相沉积或等离子体增强化学气相沉积。然后加热晶片，使得与硅膜接触的钨转化为硅化钨。在本发明的一个优选实施例中，只允许一部分硅膜与钨层的边缘反应。通过在炉或快速热处理室中对晶片O 2进行处理，将硅膜的其余部分转化为二氧化硅。或者，通过在等离子体反应器中使晶片经受O 2或O 3，硅膜的其余部分可以转化为二氧化硅。在该方法的替代但等同的实施方案中，钨金属转化为硅化钨，并且使用单件设备将剩余的硅膜转化为二氧化硅。这是通过首先在含氮环境中加热晶片，然后向上升温并用氧化气氛代替含氮气氛来完成的。

28. 发明授权

US5735960A Apparatus and method to increase gas residence time in a reactor 失效
标题翻译：在反应器中增加气体停留时间的装置和方法
公开(公告)号：US5735960A
公开(公告)日：1998-04-07
申请号：US627677
申请日：1996-04-02
申请人： Gurtej S. Sandhu , Ravi Iyer , Sujit Sharan
发明人： Gurtej S. Sandhu , Ravi Iyer , Sujit Sharan
IPC分类号： C23C16/44 , C23C16/455 , C23C16/509 , C23C16/00
CPC分类号： C23C16/45517 , C23C16/4412 , C23C16/455 , C23C16/45591 , C23C16/509
摘要： An apparatus is provided for controlling the flow of gaseous reactants in a CVD reactor through the use of a body having interior and exterior regions, in which the body defines at least one flow path between the interior and exterior regions so as to create a pressure drop from the interior to the exterior of the body within the chamber. The body is disposed in a reaction chamber with a first area proximate a gaseous reactant inlet and a second area proximate a substrate support such that the substrate is positioned in proximity to the interior of the body. As such, gaseous reactants introduced into the interior of said chamber through the inlet create a pressure drop between the interior and the exterior of the body. In a preferred embodiment, the body is cylindrically shaped and contains perforations providing the flow paths. Preferably, the perforations are either more numerous or larger in the second area than the first area to create a pressure gradient in the interior of the body. Alternatively, the perforations may be uniform in size and uniformly distributed over the body or the perforations can be configured to create a desired pressure differential in the body to support a plasma created in the body and control its location.
摘要翻译：提供了一种用于通过使用具有内部和外部区域的主体来控制CVD反应器中的气态反应物的流动的装置，其中主体限定了内部和外部区域之间的至少一个流动路径，以便产生压降从室内的内部到外部。身体设置在具有接近气体反应物入口的第一区域和接近基底支撑件的第二区域的反应室中，使得基底定位在身体内部附近。因此，通过入口引入所述室的内部的气态反应物在主体的内部和外部之间产生压降。在优选实施例中，主体是圆柱形的并且包含提供流动路径的穿孔。优选地，穿孔在第二区域中比第一区域更多或更大，以在身体的内部产生压力梯度。或者，穿孔的尺寸可以是均匀的并且均匀地分布在身体上，或者穿孔可以被配置成在身体中产生期望的压力差，以支撑在体内产生的等离子体并控制其位置。

29. 发明授权

US5733816A Method for depositing a tungsten layer on silicon 失效
标题翻译：在硅上沉积钨层的方法
公开(公告)号：US5733816A
公开(公告)日：1998-03-31
申请号：US572164
申请日：1995-12-13
申请人： Ravi Iyer , Irina Vasilyeva
发明人： Ravi Iyer , Irina Vasilyeva
IPC分类号： H01L21/28 , H01L21/285
CPC分类号： H01L21/28556 , H01L21/28061
摘要： This invention is a process for depositing tungsten metal on a silicon surface with the deposited layer having improved uniformity of thickness over prior art deposition techniques. The process involves the steps of removing any native silicon dioxide present on the silicon surface, forming a barrier layer which overlies the silicon surface which prevents the upward diffusion of silicon atoms from the polycrystalline surface, and depositing a final tungsten metal layer on top of the barrier layer. The barrier layer is preferably a refractory metal nitride. It may be formed directly by chemical vapor deposition, by reactive sputtering, or it may be formed indirectly by depositing a preliminary tungsten metal layer, subjecting the preliminary layer to a plasma formed from NH.sub.3 and N.sub.2 gases. Both preliminary and final tungsten metal layers are deposited preferably via chemical vapor deposition using the WF.sub.6 and SiH.sub.4 as reactants.
摘要翻译：本发明是一种在硅表面上沉积钨金属的方法，其中沉积层的厚度与现有技术的沉积技术相比具有改进的厚度均匀性。该方法包括去除存在于硅表面上的任何天然二氧化硅的步骤，形成覆盖在硅表面上的阻挡层，其阻止硅原子从多晶表面向上扩散，以及将最终钨金属层沉积在阻挡层。阻挡层优选为难熔金属氮化物。它可以通过化学气相沉积，通过反应溅射直接形成，或者可以通过沉积初步钨金属层，使预备层对由NH 3和N 2气体形成的等离子体进行间接形成。预先和最终的钨金属层优选通过化学气相沉积法使用WF6和SiH4作为反应物沉积。

30. 发明授权

US5665644A Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry 失效
标题翻译：形成导电互连线和集成电路的半导体处理方法
公开(公告)号：US5665644A
公开(公告)日：1997-09-09
申请号：US552880
申请日：1995-11-03
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/522 , H01L21/44
CPC分类号： H01L21/768 , H01L21/76838 , H01L23/5222 , H01L2924/0002
摘要： A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the interconnect line over the etched second insulating material. The method further comprises provision of a base electrically conductive layer beneath the first insulating material, with the anisotropically etching step etching through the first insulating material to the base conductive layer, and the conductive layer being provided in electrical connection with the base conductive layer. Integrated circuitry produced by the method and other methods is also disclosed.
摘要翻译：一种形成具有主要与其共同延伸的导电覆盖层的导电互连线的半导体处理方法包括：a）在第一电绝缘材料上提供导电互连线，该线具有顶部和侧壁; b）在所述互连线和所述第一绝缘材料上选择性地沉积第二电绝缘材料层，所述第二电绝缘材料层以在所述互连线上方沉积更大厚度的所述第二绝缘材料的厚度大于所述第一绝缘材料上所述第二绝缘材料的厚度; c）将第二绝缘材料层向内各向异性地蚀刻至少至少第一绝缘材料，同时将第二绝缘材料留在互连线的顶部和侧壁上; 以及d）在各向异性蚀刻的第二绝缘层上方设置导电层，以形成导电层，该导电层与蚀刻的第二绝缘材料上的互连线主要共同延伸。该方法还包括在第一绝缘材料下面提供基底导电层，各向异性蚀刻步骤通过第一绝缘材料蚀刻到基底导电层，并且导电层设置成与基底导电层电连接。还公开了通过该方法和其它方法生产的集成电路。

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