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    • 51. 发明授权
    • Photodiode module and apparatus including multiple photodiode modules
    • 光电二极管模块和包括多个光电二极管模块的设备
    • US07964925B2
    • 2011-06-21
    • US11654046
    • 2007-01-17
    • David FattalJason BlackstockDuncan Stewart
    • David FattalJason BlackstockDuncan Stewart
    • H01L31/06H01L27/14
    • H01L31/02024H01L27/1446H01L31/02162H01L31/022408H01L31/1085
    • Various embodiments of the present invention are directed to a photodiode module including a structure configured to selectively couple light to a dielectric-surface mode of a photonic crystal of the photodiode module. In one embodiment of the present invention, a photodiode module includes a semiconductor structure having a p-region and an n-region. The photodiode module further includes a photonic crystal having a surface positioned adjacent to the semiconductor structure. A diffraction grating of the photodiode module may be positioned and configured to selectively couple light incident on the diffraction grating to a dielectric-surface mode associated with the surface of the photonic crystal. In another embodiment of the present invention, a photodiode apparatus includes multiple, stacked photodiode modules, each of which is configured to selectively absorb light at a selected wavelength or range of wavelengths.
    • 本发明的各种实施例涉及一种光电二极管模块,其包括被配置为选择性地将光耦合到光电二极管模块的光子晶体的电介质表面模式的结构。 在本发明的一个实施例中,光电二极管模块包括具有p区和n区的半导体结构。 光电二极管模块还包括具有邻近半导体结构定位的表面的光子晶体。 可以将光电二极管模块的衍射光栅定位和配置为将入射在衍射光栅上的光选择性地耦合到与光子晶体的表面相关联的电介质表面模式。 在本发明的另一实施例中,光电二极管装置包括多个堆叠的光电二极管模块,每个光电二极管模块被配置为选择性地吸收所选择的波长或波长范围的光。
    • 55. 发明申请
    • Method For Connecting Multicore Fibers To Optical Devices
    • 将多芯纤维连接到光器件的方法
    • US20090180734A1
    • 2009-07-16
    • US12254490
    • 2008-10-20
    • Marco FiorentinoRaymond BeausoleiDuncan Stewart
    • Marco FiorentinoRaymond BeausoleiDuncan Stewart
    • G02B6/26
    • G02B6/43G02B6/02042G02B6/4249
    • A method for connecting a photonic crystal fiber having a plurality of cores connected to an optical device. An end of the photonic crystal fiber may be placed on a surface of an optical device having a plurality of coupling pads. A first core of the end of the photonic crystal fiber may be positioned over a first coupling pad on the optical device to enable a threshold amount of a coherent beam of light to propagate through the first core and first coupling pad. A second core of the end of the photonic crystal fiber is aligned to a second coupling pad on the optical device to enable a threshold amount of another coherent beam of light to propagate through the second core and second coupling pad. The end of the photonic crystal fiber may be adhered to the surface of the optical device while the position of the first and the second cores relative to the first and the second coupling pads, respectively, is maintained.
    • 一种用于连接具有连接到光学装置的多个芯的光子晶体光纤的方法。 光子晶体光纤的端部可以放置在具有多个耦合焊盘的光学器件的表面上。 光子晶体光纤的端部的第一核可以被定位在光学器件上的第一耦合焊盘上方,以使阈值量的相干光束能够通过第一芯和第一耦合焊盘传播。 光子晶体光纤的端部的第二核心与光学器件上的第二耦合焊盘对准,以使另一相干光束的阈值能够传播通过第二芯片和第二耦合焊盘。 光子晶体光纤的端部可以粘附到光学器件的表面,同时保持第一和第二芯部相对于第一和第二耦合焊盘的位置。
    • 58. 发明授权
    • Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
    • 基于隧道电阻器结的微米级/纳米级解复用器阵列
    • US07319416B2
    • 2008-01-15
    • US11343325
    • 2006-01-30
    • Warren RobinettGregory S. SniderDuncan StewartJoseph Straznicky
    • Warren RobinettGregory S. SniderDuncan StewartJoseph Straznicky
    • H03M7/14
    • G11C8/10G11C13/0023H03M13/51
    • Various embodiments of the present invention are directed to demultiplexers that include tunneling resistor nanowire junctions, and to nanowire addressing methods for reliably addressing nanowire signal lines in nanoscale and mixed-scale demultiplexers. In one embodiment of the present invention, an encoder-demultiplexer comprises a number of input signal lines and an encoder that generates an n-bit-constant-weight-code code-word internal address for each different input address received on the input signal lines. The encoder-demultiplexer includes n microscale signal lines on which an n-bit-constant-weight-code code-word internal address is output by the encoder, where each microscale signal line carries one bit of the n-bit-constant-weight-code code-word internal address. The encoder-demultiplexer also includes a number of encoder-demultiplexer-addressed nanowire signal lines interconnected with the n microscale signal lines via tunneling resistor junctions, the encoder-demultiplexer-addressed nanowire signal lines each associated with an n-bit-constant-weight-code code-word internal address.
    • 本发明的各种实施例涉及包括隧穿电阻器纳米线结的解复用器,以及纳米线寻址方法,用于在纳米尺度和混合尺度解复用器中可靠地寻址纳米线信号线。 在本发明的一个实施例中,编码器 - 解复用器包括多个输入信号线和一个编码器,其生成在输入信号线上接收的每个不同输入地址的n位恒权重码码字内部地址 。 编码器 - 解复用器包括n个微米级信号线,编码器输出n位恒定权重码码字内部地址,其中每个微信号线承载n位恒权重码内部地址的一位, 代码字内部地址。 编码器 - 解复用器还包括通过隧道电阻器结与n个微米级信号线互连的多个编码器 - 解复用器寻址的纳米线信号线,编码器 - 解复用器寻址的纳米线信号线每个与n比特恒权重信号线相关联, 代码字内部地址。
    • 60. 发明申请
    • NANOSCALE LATCH-ARRAY PROCESSING ENGINES
    • NANOSCALE LATCH-ARRAY加工发动机
    • US20070109014A1
    • 2007-05-17
    • US11192197
    • 2005-07-27
    • Gregory SniderPhilip KuekesDuncan Stewart
    • Gregory SniderPhilip KuekesDuncan Stewart
    • H03K19/173
    • B82Y10/00G06N99/007H01L27/101
    • One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions. Nanoscale-latch arrays can be combined and interconnected in an almost limitless number of different ways to construct arbitrarily complex, sequential, parallel, or both parallel and sequential computing engines that represent additional embodiments of the present invention.
    • 本发明的一个实施例是通过纳米线总线互连以形成锁存阵列的纳米级锁存器的阵列。 纳米尺度锁存阵列中的每个纳米级锁存器用作纳米尺度寄存器,并由纳米尺度控制线驱动。 锁存阵列的原始操作可以被定义为一个或多个输入到纳米线数据总线和纳米尺度控制线中的一个或多个的序列。 在本发明的各种锁存阵列实施例中,可以以受控的方式将信息从一个纳米级锁存器传送到另一个纳米级锁存器,并且可以设计信息传送操作的序列以实现任意的布尔逻辑运算,并且运算符包括NOT, AND,OR,XOR,NOR,NAND和其他这样的布尔逻辑运算符和操作,以及输入和输出功能。 纳秒级锁存器阵列可以以几乎无限数量的不同方式组合和互连,以构造代表本发明附加实施例的任意复杂,顺序,并行或并行和顺序的计算引擎。