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51. 发明授权

US06204175B1 Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer 有权
$Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer$
标题翻译：在难熔金属氮化物层上沉积光滑的保形铝膜的方法
公开(公告)号：US06204175B1
公开(公告)日：2001-03-20
申请号：US09226053
申请日：1999-01-05
申请人： Gilbert Lai , Gurtej S. Sandhu , Ravi Iyer , Brian A. Vaartstra
发明人： Gilbert Lai , Gurtej S. Sandhu , Ravi Iyer , Brian A. Vaartstra
IPC分类号： H01L2144
CPC分类号： H01L21/28568 , C23C16/0272 , C23C16/44 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76877
摘要： A method of forming a conformal aluminum film on a refractory metal nitride layer is provided and includes positioning a substrate having the refractory metal nitride layer thereon within a chemical vapor deposition chamber; establishing a nominal temperature for the substrate; introducing a carrier gas containing a gaseous, metalorganic precursor into the chamber for a time sufficient to form a metallic seed layer; and introducing a carrier gas containing a gaseous aluminum metalorganic precursor into the chamber for a time sufficient to form a conformal aluminum metal film over the metal refractory nitride layer.
摘要翻译：提供了在难熔金属氮化物层上形成共形铝膜的方法，包括将其上具有难熔金属氮化物层的基板定位在化学气相沉积室内; 建立基板的标称温度; 将含有气态金属有机前体的载气引入室中足以形成金属种子层的时间; 并将含有气态铝金属有机前体的载气引入室中足以在金属耐火氮化物层上形成共形铝金属膜的时间。

52. 发明授权

US6162499A Method of inhibiting deposition of material on an internal wall of a chemical vapor deposition reactor 有权
标题翻译：抑制材料沉积在化学气相沉积反应器的内壁上的方法
公开(公告)号：US6162499A
公开(公告)日：2000-12-19
申请号：US144484
申请日：1998-08-31
申请人： Gurtej S. Sandhu , Ravi Iyer , Donald L. Westmoreland
发明人： Gurtej S. Sandhu , Ravi Iyer , Donald L. Westmoreland
IPC分类号： C23C16/44 , B05D7/22 , C23C16/00
CPC分类号： C23C16/4404
摘要： A method of inhibiting deposition of material on a wall of a chemical vapor deposition reactor includes providing a chemical vapor deposition reactor having a wall which has an inside facing surface, the inside facing surface at least partially defining a chemical vapor deposition reactor chamber; forming a first material atop the inside facing surface; positioning a substrate in the chemical vapor deposition a reactor chamber, the substrate having an outer surface; and chemical vapor depositing a second material layer on the substrate in a manner which is selective to the substrate outer surface, and not the first material, thereby restricting deposition of the second layer on the reactor inside facing surface.
摘要翻译：一种抑制材料沉积在化学气相沉积反应器的壁上的方法包括提供具有壁的化学气相沉积反应器，所述壁具有面向内的表面，所述内表面至少部分地限定化学气相沉积反应室; 在面向内表面的顶部形成第一材料; 将基板定位在化学气相沉积中的反应室，所述基板具有外表面; 以及以对衬底外表面有选择性的方式在衬底上沉积第二材料层，而不是第一材料，由此限制第二层在反应器面对表面上的沉积。

53. 发明授权

US6156630A Titanium boride gate electrode and interconnect and methods regarding same 失效
公开(公告)号：US6156630A
公开(公告)日：2000-12-05
申请号：US916275
申请日：1997-08-22
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L21/28 , H01L21/768 , H01L29/49 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/76895
摘要： A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.

54. 发明授权

US6121133A Isolation using an antireflective coating 失效
公开(公告)号：US6121133A
公开(公告)日：2000-09-19
申请号：US916276
申请日：1997-08-22
申请人： Ravi Iyer , Steven M. McDonald , Thomas R. Glass , Zhiping Yin
发明人： Ravi Iyer , Steven M. McDonald , Thomas R. Glass , Zhiping Yin
IPC分类号： G03F7/11 , G03F7/09 , H01L21/027 , H01L21/316 , H01L21/32 , H01L21/76 , H01L21/762 , H01L21/4763
CPC分类号： G03F7/091 , G03F7/092 , H01L21/0276 , H01L21/32 , H01L21/76202 , Y10T428/24471 , Y10T428/24917
摘要： A method of forming an oxidation diffusion barrier stack for use in fabrication of integrated circuits includes forming an inorganic antireflective material layer on a semiconductor substrate assembly with an oxidation diffusion barrier layer then formed on the inorganic antireflective material layer. Another method of forming such a stack includes forming a pad oxide layer on the semiconductor substrate assembly with an inorganic antireflective material layer then formed on the pad oxide layer and an oxidation diffusion barrier layer formed on the antireflective material layer. Another method of forming the stack includes forming a pad oxide layer on the semiconductor substrate assembly. A first oxidation diffusion barrier layer is then formed on the pad oxide layer, an inorganic antireflective material layer is formed on the first oxidation diffusion barrier layer, and a second oxidation diffusion barrier layer is formed on the inorganic antireflective material layer. The antireflective material layer may include a layer of material selected from the group of silicon nitride, silicon oxide, and silicon oxynitride and further may be a silicon-rich layer. The oxidation diffusion barrier stacks may be used for oxidation of field regions for isolation in an integration circuit. Further, the various oxidation diffusion barrier stacks are also described.

55. 发明授权

US6001541A Method of forming contact openings and contacts 失效
标题翻译：形成接触开口和触点的方法
公开(公告)号：US6001541A
公开(公告)日：1999-12-14
申请号：US49970
申请日：1998-03-27
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76814 , H01L21/31144
摘要： The invention comprises methods of forming contact openings and methods of forming contacts. In but one implementation, an inorganic antireflective coating material layer is formed over an insulating material layer. A contact opening is etched through the inorganic antireflective coating layer and into the insulating layer. Insulative material within the contact opening is etched and a projection of inorganic antireflective coating material is formed within the contact opening. The inorganic antireflective coating material is etched to substantially remove the projection from the contact opening. The preferred etching to remove the projection is facet etching, most preferably plasma etching. The preferred inorganic antireflective coating material is selected from the group consisting of SiO.sub.x where "x" ranges from 0.1 to 1.8, SiN.sub.y where "y" ranges from 0.1 to 1.2, and SiO.sub.x N.sub.y where "x" ranges from 0.2 to 1.8 and "y" ranges from 0.01 to 1.0, and mixtures thereof. In another implementation, only a portion of the inorganic antireflective coating layer is removed from over the insulating material layer after initially etching the contact opening. After removing the portion of the inorganic antireflective coating layer, the insulating material layer is etched to widen at least a portion of the contact opening. The invention also contemplates use of organic antireflective coating layers.
摘要翻译：本发明包括形成接触开口的方法和形成接触的方法。但是在一个实施方式中，在绝缘材料层上形成无机抗反射涂层层。通过无机抗反射涂层蚀刻接触开口并进入绝缘层。蚀刻接触开口内的绝缘材料，并且在接触开口内形成无机抗反射涂层材料的突起。对无机抗反射涂层材料进行蚀刻以基本上从接触开口移除突起。去除突起的优选蚀刻是刻面蚀刻，最优选等离子体蚀刻。优选的无机抗反射涂层材料选自SiO x，其中“x”为0.1至1.8，SiN y其中“y”为0.1至1.2，SiO x N y为“x”为0.2至1.8，“y” 范围为0.01至1.0，以及它们的混合物。在另一个实施方案中，在最初蚀刻接触开口之后，仅在绝缘材料层上除去无机抗反射涂层的一部分。在去除无机抗反射涂层的部分之后，绝缘材料层被蚀刻以加宽接触开口的至少一部分。本发明还考虑使用有机抗反射涂层。

56. 发明授权

US5981380A Method of forming a local interconnect including selectively etched conductive layers and recess formation 失效
公开(公告)号：US5981380A
公开(公告)日：1999-11-09
申请号：US27537
申请日：1998-02-23
申请人： Jigish D. Trivedi , Ravi Iyer
发明人： Jigish D. Trivedi , Ravi Iyer
IPC分类号： H01L21/60 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/45 , H01L21/70
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76846 , H01L21/7685 , H01L21/76855 , H01L21/76856 , H01L21/76864 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/53223 , H01L23/53238 , H01L23/53257 , H01L29/456 , H01L2221/1078 , H01L2924/0002
摘要： A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. A photoresist layer is then formed over the hard mask layer. The hard mask layer is selectively removed from above an adjacent gate stack on the semiconductor substrate using an etch that is selective to the first barrier layer. The first barrier layer is selectively removed using an etch that is selective to the hard mask layer. A silica layer is formed over the hard mask layer. A recess is formed in the silica layer that is aligned with an active area within the semiconductor substrate. The recess is filled with an electrically conductive material. A second method of forming a local interconnect structure is provided comprising forming a first barrier layer comprising sputter titanium nitride over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. A first electrically conductive layer comprising tungsten is then formed over the first barrier layer using chemical vapor deposition. The first electrically conductive layer provides good step coverage over the topographical structure. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer. A hard mask layer comprising polysilicon or silica is then formed over the second barrier layer. The hard mask is selectively removed from above an adjacent gate stack on the semiconductor substrate with an etch that is selective to the second barrier layer. The second barrier layer, the first conductive layer, and the first barrier layer are selectively removed, thereby exposing the underlying gate stack on the semiconductor substrate using a chemical etch selective to the hard mask layer. A silica layer is then formed with a recess therein that is filled with an electrically conductive material to form an active area contact through the local interconnect structure.

57. 发明授权

US5935336A Apparatus to increase gas residence time in a reactor 失效
公开(公告)号：US5935336A
公开(公告)日：1999-08-10
申请号：US950549
申请日：1997-10-15
申请人： Gurtej S. Sandhu , Ravi Iyer , Sujit Sharan
发明人： Gurtej S. Sandhu , Ravi Iyer , Sujit Sharan
IPC分类号： C23C16/44 , C23C16/455 , C23C16/509 , C23C16/00
CPC分类号： C23C16/45517 , C23C16/4412 , C23C16/455 , C23C16/45591 , C23C16/509
摘要： An apparatus is provided for controlling the flow of gaseous reactants in a CVD reactor through the use of a body having interior and exterior regions, in which the body defines at least one flow path between the interior and exterior regions so as to create a pressure drop from the interior to the exterior of the body within the chamber. The body is disposed in a reaction chamber with a first area proximate a gaseous reactant inlet and a second area proximate a substrate support such that the substrate is positioned in proximity to the interior of the body. As such, gaseous reactants introduced into the interior of said chamber through the inlet create a pressure drop between the interior and the exterior of the body. In a preferred embodiment, the body is cylindrically shaped and contains perforations providing the flow paths. Preferably, the perforations are either more numerous or larger in the second area than the first area to create a pressure gradient in the interior of the body. Alternatively, the perforations may be uniform in size and uniformly distributed over the body or the perforations can be configured to create a desired pressure differential in the body to support a plasma created in the body and control its location.

58. 发明授权

US5910684A Integrated circuitry 失效
标题翻译：集成电路
公开(公告)号：US5910684A
公开(公告)日：1999-06-08
申请号：US708116
申请日：1996-09-03
申请人： Gurtej S. Sandhu , Ravi Iyer
发明人： Gurtej S. Sandhu , Ravi Iyer
IPC分类号： H01L21/768 , H01L23/522 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/768 , H01L21/76838 , H01L23/5222 , H01L2924/0002
摘要： A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the interconnect line over the etched second insulating material. The method further comprises provision of a base electrically conductive layer beneath the first insulating material, with the anisotropically etching step etching through the first insulating material to the base conductive layer, and the conductive layer being provided in electrical connection with the base conductive layer. Integrated circuitry produced by the method and other methods is also disclosed.
摘要翻译：一种形成具有与其主要共同延伸的导电覆盖层的导电互连线的半导体处理方法包括：a）在第一电绝缘材料上提供导电互连线，该线具有顶部和侧壁; b）在所述互连线和所述第一绝缘材料上选择性地沉积第二电绝缘材料层，所述第二电绝缘材料层以在所述互连线上方沉积更大厚度的所述第二绝缘材料的厚度大于所述第一绝缘材料上所述第二绝缘材料的厚度; c）将第二绝缘材料层向内各向异性地蚀刻至少至少第一绝缘材料，同时将第二绝缘材料留在互连线的顶部和侧壁上; 以及d）在各向异性蚀刻的第二绝缘层上方设置导电层，以形成导电层，该导电层主要与蚀刻的第二绝缘材料上的互连线共同延伸。该方法还包括在第一绝缘材料下面提供基底导电层，各向异性蚀刻步骤通过第一绝缘材料蚀刻到基底导电层，并且导电层设置成与基底导电层电连接。还公开了通过该方法和其它方法生产的集成电路。

59. 发明授权

US5856236A Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer 失效
$Method of depositing a smooth conformal aluminum film on a refractory metal nitride layer$
标题翻译：在难熔金属氮化物层上沉积光滑的保形铝膜的方法
公开(公告)号：US5856236A
公开(公告)日：1999-01-05
申请号：US663996
申请日：1996-06-14
申请人： Gilbert Lai , Gurtej S. Sandhu , Ravi Iyer , Brian A. Vaartstra
发明人： Gilbert Lai , Gurtej S. Sandhu , Ravi Iyer , Brian A. Vaartstra
IPC分类号： C23C16/02 , C23C16/44 , H01L21/285 , H01L21/768 , H01L21/44
CPC分类号： H01L21/28568 , C23C16/0272 , C23C16/44 , H01L21/28518 , H01L21/28556 , H01L21/28562 , H01L21/76877
摘要： A method of forming a conformal aluminum film on a refractory metal nitride layer is provided and includes positioning a substrate having the refractory metal nitride layer thereon within a chemical vapor deposition chamber; establishing a nominal temperature for the substrate; introducing a carrier gas containing a gaseous, metalorganic precursor into the chamber for a time sufficient to form a metallic seed layer; and introducing a carrier gas containing a gaseous aluminum metalorganic precursor into the chamber for a time sufficient to form a conformal aluminum metal film over the metal refractory nitride layer.
摘要翻译：提供了在难熔金属氮化物层上形成共形铝膜的方法，包括将其上具有难熔金属氮化物层的基板定位在化学气相沉积室内; 建立基板的标称温度; 将含有气态金属有机前体的载气引入室中足以形成金属种子层的时间; 并将含有气态铝金属有机前体的载气引入室中足以在金属耐火氮化物层上形成共形铝金属膜的时间。

60. 发明授权

US5382550A Method of depositing SiO.sub.2 on a semiconductor substrate 失效
标题翻译：在半导体衬底上沉积SiO 2的方法
公开(公告)号：US5382550A
公开(公告)日：1995-01-17
申请号：US103392
申请日：1993-08-05
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L21/316 , H01L21/02
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/31612 , H01L21/31633 , Y10S148/118
摘要： A deposition method of reducing fixed charge in a layer of silicon dioxide includes: a) providing a gaseous organosilicon compound to a chemical vapor deposition reactor having a semiconductor wafer positioned therein; b) providing an oxidizing gas to the reactor for reaction with the organosilicon compound; c) feeding a gaseous hydrogen containing source to the reactor; and d) reacting the organosilicon compound, oxidizing gas and gaseous hydrogen containing source to deposit a layer of silicon dioxide on the wafer, the hydrogen containing source gas effectively reacting with the organosilicon compound to produce reduced fixed charge in the deposited silicon dioxide layer over that which would be present if no hydrogen containing source gas were fed to the reactor under otherwise identical reacting conditions. Another method of depositing a layer of silicon dioxide on a semiconductor wafer comprises: a) providing a gaseous organosilicon compound to a chemical vapor deposition reactor having a semiconductor wafer positioned therein; and b) providing an oxidizing gas to the reactor, and reacting the oxidizing gas with the gaseous organosilicon compound in the reactor to deposit a layer of silicon dioxide on the wafer, the oxidizing gas comprising a compound having an N--O bond.
摘要翻译：减少二氧化硅层中的固定电荷的沉积方法包括：a）向其中定位有半导体晶片的化学气相沉积反应器提供气态有机硅化合物; b）向反应器提供氧化气体以与有机硅化合物反应; c）将含气态的氢气源送入反应器; 和d）使有机硅化合物，氧化气体和含氢气气体源反应以在晶片上沉积二氧化硅层，含氢源气体与有机硅化合物有效反应以在沉积的二氧化硅层中产生减少的固定电荷，超过该沉积二氧化硅层如果在其他相同的反应条件下不将含氢的源气体进料到反应器中，则其将存在。在半导体晶片上沉积二氧化硅层的另一种方法包括：a）向其中定位有半导体晶片的化学气相沉积反应器提供气态有机硅化合物; 和b）向所述反应器提供氧化气体，并且使所述氧化气体与所述反应器中的所述气态有机硅化合物反应以在所述晶片上沉积二氧化硅层，所述氧化气体包含具有N-O键的化合物。

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