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    • 55. 发明授权
    • Method of forming contact openings and contacts
    • 形成接触开口和触点的方法
    • US6001541A
    • 1999-12-14
    • US49970
    • 1998-03-27
    • Ravi Iyer
    • Ravi Iyer
    • H01L21/311H01L21/768H01L21/00
    • H01L21/76814H01L21/31144
    • The invention comprises methods of forming contact openings and methods of forming contacts. In but one implementation, an inorganic antireflective coating material layer is formed over an insulating material layer. A contact opening is etched through the inorganic antireflective coating layer and into the insulating layer. Insulative material within the contact opening is etched and a projection of inorganic antireflective coating material is formed within the contact opening. The inorganic antireflective coating material is etched to substantially remove the projection from the contact opening. The preferred etching to remove the projection is facet etching, most preferably plasma etching. The preferred inorganic antireflective coating material is selected from the group consisting of SiO.sub.x where "x" ranges from 0.1 to 1.8, SiN.sub.y where "y" ranges from 0.1 to 1.2, and SiO.sub.x N.sub.y where "x" ranges from 0.2 to 1.8 and "y" ranges from 0.01 to 1.0, and mixtures thereof. In another implementation, only a portion of the inorganic antireflective coating layer is removed from over the insulating material layer after initially etching the contact opening. After removing the portion of the inorganic antireflective coating layer, the insulating material layer is etched to widen at least a portion of the contact opening. The invention also contemplates use of organic antireflective coating layers.
    • 本发明包括形成接触开口的方法和形成接触的方法。 但是在一个实施方式中,在绝缘材料层上形成无机抗反射涂层层。 通过无机抗反射涂层蚀刻接触开口并进入绝缘层。 蚀刻接触开口内的绝缘材料,并且在接触开口内形成无机抗反射涂层材料的突起。 对无机抗反射涂层材料进行蚀刻以基本上从接触开口移除突起。 去除突起的优选蚀刻是刻面蚀刻,最优选等离子体蚀刻。 优选的无机抗反射涂层材料选自SiO x,其中“x”为0.1至1.8,SiN y其中“y”为0.1至1.2,SiO x N y为“x”为0.2至1.8,“y” 范围为0.01至1.0,以及它们的混合物。 在另一个实施方案中,在最初蚀刻接触开口之后,仅在绝缘材料层上除去无机抗反射涂层的一部分。 在去除无机抗反射涂层的部分之后,绝缘材料层被蚀刻以加宽接触开口的至少一部分。 本发明还考虑使用有机抗反射涂层。
    • 56. 发明授权
    • Method of forming a local interconnect including selectively etched
conductive layers and recess formation
    • US5981380A
    • 1999-11-09
    • US27537
    • 1998-02-23
    • Jigish D. TrivediRavi Iyer
    • Jigish D. TrivediRavi Iyer
    • H01L21/60H01L21/768H01L23/485H01L23/532H01L29/45H01L21/70
    • H01L21/76865H01L21/76843H01L21/76846H01L21/7685H01L21/76855H01L21/76856H01L21/76864H01L21/76895H01L21/76897H01L23/485H01L23/53223H01L23/53238H01L23/53257H01L29/456H01L2221/1078H01L2924/0002
    • A method of forming a local interconnect structure is provided. A first barrier layer comprising sputtered titanium nitride is formed over a topographical structure situated upon a field oxide region within a semiconductor substrate. A hard mask layer comprising tungsten silicide is formed over the first barrier layer. A photoresist layer is then formed over the hard mask layer. The hard mask layer is selectively removed from above an adjacent gate stack on the semiconductor substrate using an etch that is selective to the first barrier layer. The first barrier layer is selectively removed using an etch that is selective to the hard mask layer. A silica layer is formed over the hard mask layer. A recess is formed in the silica layer that is aligned with an active area within the semiconductor substrate. The recess is filled with an electrically conductive material. A second method of forming a local interconnect structure is provided comprising forming a first barrier layer comprising sputter titanium nitride over a semiconductor substrate having a topographical structure situated upon a field oxide region within the semiconductor substrate. A first electrically conductive layer comprising tungsten is then formed over the first barrier layer using chemical vapor deposition. The first electrically conductive layer provides good step coverage over the topographical structure. A second barrier layer comprising sputtered titanium nitride is formed over the first electrically conductive layer. A hard mask layer comprising polysilicon or silica is then formed over the second barrier layer. The hard mask is selectively removed from above an adjacent gate stack on the semiconductor substrate with an etch that is selective to the second barrier layer. The second barrier layer, the first conductive layer, and the first barrier layer are selectively removed, thereby exposing the underlying gate stack on the semiconductor substrate using a chemical etch selective to the hard mask layer. A silica layer is then formed with a recess therein that is filled with an electrically conductive material to form an active area contact through the local interconnect structure.
    • 58. 发明授权
    • Integrated circuitry
    • 集成电路
    • US5910684A
    • 1999-06-08
    • US708116
    • 1996-09-03
    • Gurtej S. SandhuRavi Iyer
    • Gurtej S. SandhuRavi Iyer
    • H01L21/768H01L23/522H01L23/48H01L23/52H01L29/40
    • H01L21/768H01L21/76838H01L23/5222H01L2924/0002
    • A semiconductor processing method of forming an electrically conductive interconnect line having an electrical conductive covering predominately coextensive therewith, includes, a) providing an conductive interconnect line over a first electrically insulating material, the line having a top and sidewalls; b) selectively depositing a second electrically insulating material layer over the interconnect line and the first insulating material in a manner which deposits a greater thickness of the second insulating material atop the interconnect line than a thickness of the second insulating material over the first insulating material; c) anisotropically etching the second insulating material layer inwardly to at least the first insulating material yet leaving second insulating material over the top and the sidewalls of the interconnect line; and d) providing an electrically conductive layer over the anisotropically etched second insulating layer to form a conductive layer which is predominately coextensive with the interconnect line over the etched second insulating material. The method further comprises provision of a base electrically conductive layer beneath the first insulating material, with the anisotropically etching step etching through the first insulating material to the base conductive layer, and the conductive layer being provided in electrical connection with the base conductive layer. Integrated circuitry produced by the method and other methods is also disclosed.
    • 一种形成具有与其主要共同延伸的导电覆盖层的导电互连线的半导体处理方法包括:a)在第一电绝缘材料上提供导电互连线,该线具有顶部和侧壁; b)在所述互连线和所述第一绝缘材料上选择性地沉积第二电绝缘材料层,所述第二电绝缘材料层以在所述互连线上方沉积更大厚度的所述第二绝缘材料的厚度大于所述第一绝缘材料上所述第二绝缘材料的厚度; c)将第二绝缘材料层向内各向异性地蚀刻至少至少第一绝缘材料,同时将第二绝缘材料留在互连线的顶部和侧壁上; 以及d)在各向异性蚀刻的第二绝缘层上方设置导电层,以形成导电层,该导电层主要与蚀刻的第二绝缘材料上的互连线共同延伸。 该方法还包括在第一绝缘材料下面提供基底导电层,各向异性蚀刻步骤通过第一绝缘材料蚀刻到基底导电层,并且导电层设置成与基底导电层电连接。 还公开了通过该方法和其它方法生产的集成电路。
    • 60. 发明授权
    • Method of depositing SiO.sub.2 on a semiconductor substrate
    • 在半导体衬底上沉积SiO 2的方法
    • US5382550A
    • 1995-01-17
    • US103392
    • 1993-08-05
    • Ravi Iyer
    • Ravi Iyer
    • H01L21/316H01L21/02
    • H01L21/02164H01L21/02211H01L21/02216H01L21/02274H01L21/31612H01L21/31633Y10S148/118
    • A deposition method of reducing fixed charge in a layer of silicon dioxide includes: a) providing a gaseous organosilicon compound to a chemical vapor deposition reactor having a semiconductor wafer positioned therein; b) providing an oxidizing gas to the reactor for reaction with the organosilicon compound; c) feeding a gaseous hydrogen containing source to the reactor; and d) reacting the organosilicon compound, oxidizing gas and gaseous hydrogen containing source to deposit a layer of silicon dioxide on the wafer, the hydrogen containing source gas effectively reacting with the organosilicon compound to produce reduced fixed charge in the deposited silicon dioxide layer over that which would be present if no hydrogen containing source gas were fed to the reactor under otherwise identical reacting conditions. Another method of depositing a layer of silicon dioxide on a semiconductor wafer comprises: a) providing a gaseous organosilicon compound to a chemical vapor deposition reactor having a semiconductor wafer positioned therein; and b) providing an oxidizing gas to the reactor, and reacting the oxidizing gas with the gaseous organosilicon compound in the reactor to deposit a layer of silicon dioxide on the wafer, the oxidizing gas comprising a compound having an N--O bond.
    • 减少二氧化硅层中的固定电荷的沉积方法包括:a)向其中定位有半导体晶片的化学气相沉积反应器提供气态有机硅化合物; b)向反应器提供氧化气体以与有机硅化合物反应; c)将含气态的氢气源送入反应器; 和d)使有机硅化合物,氧化气体和含氢气气体源反应以在晶片上沉积二氧化硅层,含氢源气体与有机硅化合物有效反应以在沉积的二氧化硅层中产生减少的固定电荷,超过该沉积二氧化硅层 如果在其他相同的反应条件下不将含氢的源气体进料到反应器中,则其将存在。 在半导体晶片上沉积二氧化硅层的另一种方法包括:a)向其中定位有半导体晶片的化学气相沉积反应器提供气态有机硅化合物; 和b)向所述反应器提供氧化气体,并且使所述氧化气体与所述反应器中的所述气态有机硅化合物反应以在所述晶片上沉积二氧化硅层,所述氧化气体包含具有N-O键的化合物。