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1. 发明申请

US20160086951A1 CMOS NANOWIRE STRUCTURE 审中-公开
标题翻译： CMOS纳米结构
公开(公告)号：US20160086951A1
公开(公告)日：2016-03-24
申请号：US14948083
申请日：2015-11-20
申请人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
发明人： Seiyon Kim , Kelin J. Kuhn , Tahir Ghani , Anand S. Murthy , Annalisa Cappellani , Stephen M. Cea , Rafael Rios , Glenn A. Glass
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/423 , H01L29/06 , H01L29/10
CPC分类号： H01L21/823821 , B82Y10/00 , H01L21/8238 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/12 , H01L27/1203 , H01L27/1211 , H01L29/0673 , H01L29/0676 , H01L29/1033 , H01L29/42356 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/7853
摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.
摘要翻译：描述了免费的金属氧化物半导体纳米线结构。例如，半导体结构包括第一半导体器件。第一半导体器件包括设置在衬底之上的第一纳米线。第一纳米线具有在衬底上方的第一距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一栅极电极堆叠完全包围第一纳米线的离散通道区域。半导体结构还包括第二半导体器件。第二半导体器件包括设置在衬底上方的第二纳米线。第二纳米线在衬底上方具有第二距离的中点，并且包括在离散通道区域的任一侧上的离散沟道区域和源极和漏极区域。第一距离与第二距离不同。第二栅极电极堆叠完全围绕第二纳米线的离散通道区域。

2. 发明申请

US20150060945A1 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 审中-公开
标题翻译：具有高浓度的硼氢化锗的晶体管
公开(公告)号：US20150060945A1
公开(公告)日：2015-03-05
申请号：US14535387
申请日：2014-11-07
申请人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号： H01L29/36 , H01L21/02 , H01L29/78 , H01L29/66 , H01L29/165 , H01L29/08
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。这些技术可以例如在平面或非平面晶体管器件中实现。

3. 发明申请

US20130264639A1 COLUMN IV TRANSISTORS FOR PMOS INTEGRATION 有权
标题翻译：用于PMOS整合的柱IV晶体管
公开(公告)号：US20130264639A1
公开(公告)日：2013-10-10
申请号：US13990249
申请日：2011-12-20
申请人： Glenn A. Glass , Anand S. Murthy
发明人： Glenn A. Glass , Anand S. Murthy
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibit reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
摘要翻译：公开了用于形成具有高浓度锗的源/漏区的列IV晶体管器件的技术，并且相对于常规器件而言显示降低的寄生电阻。在一些示例性实施例中，源极/漏极区域各自包括薄的p型硅或锗或SiGe沉积，源/漏材料的其余部分沉积为p型锗或锗合金（例如，锗：锡或其他合适的应变诱导剂，并且锗含量为至少80原子％和20原子％以下的其他组分）。在某些情况下，可以在富锗盖层中观察到应变松弛的证据，包括失配位错和/或穿透位错和/或双胞胎。可以使用多个晶体管配置，包括平面和非平面晶体管结构（例如，FinFET和纳米线晶体管），以及应变和非限制的通道结构。

4. 发明申请

US20130248999A1 CONTACT RESISTANCE REDUCTION EMPLOYING GERMANIUM OVERLAYER PRE-CONTACT METALIZATION 有权
公开(公告)号：US20130248999A1
公开(公告)日：2013-09-26
申请号：US13990224
申请日：2011-09-30
申请人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
发明人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
IPC分类号： H01L29/36
CPC分类号： H01L29/36 , G11C7/1051 , G11C16/0483 , G11C16/08 , G11C16/12 , G11C16/24 , G11C16/3418 , G11C16/3431 , G11C16/3445 , G11C16/3459 , G11C2216/14 , H01L21/28518 , H01L21/28525 , H01L21/76814 , H01L29/41783 , H01L29/41791 , H01L29/45 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/7833 , H01L29/7848 , H01L29/785
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

5. 发明申请

US20130154016A1 TIN DOPED III-V MATERIAL CONTACTS 有权
标题翻译： TIN DOPED III-V材料联系
公开(公告)号：US20130154016A1
公开(公告)日：2013-06-20
申请号：US13685369
申请日：2012-11-26
申请人： Glenn A. Glass , Anand S. Murthy , Michael J. Jackson , Harold W. Kennel
发明人： Glenn A. Glass , Anand S. Murthy , Michael J. Jackson , Harold W. Kennel
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/267 , H01L21/28525 , H01L21/28568 , H01L29/165 , H01L29/207 , H01L29/42392 , H01L29/452 , H01L29/456 , H01L29/66477 , H01L29/66522 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66795 , H01L29/78 , H01L29/7833 , H01L29/785 , H01L29/78696
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstained channel structures.
摘要翻译：公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。这些技术可以例如使用诸如硅或硅锗（SiGe）源极/漏极区域上的一种或多种金属/合金的金属接触来实现。根据一个示例性实施例，在源极/漏极和接触金属之间设置中间锡掺杂的III-V材料层，以显着降低接触电阻。可以使用锡掺杂层的部分或完全氧化来进一步提高接触电阻。在一些示例情况下，锡掺杂的III-V材料层在衬底附近具有半导体相和金属接触附近的氧化物相。根据本公开，许多晶体管配置和合适的制造工艺将是显而易见的，包括平面和非平面晶体管结构（例如，FinFET，纳米线晶体管等），以及应变和未染色的通道结构。

6. 发明授权

US07833883B2 Precursor gas mixture for depositing an epitaxial carbon-doped silicon film 有权
标题翻译：用于沉积外延碳掺杂硅膜的前体气体混合物
公开(公告)号：US07833883B2
公开(公告)日：2010-11-16
申请号：US11692782
申请日：2007-03-28
申请人： Danielle M. Simonelli , Anand S. Murthy , Daniel B. Aubertine
发明人： Danielle M. Simonelli , Anand S. Murthy , Daniel B. Aubertine
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L29/7834 , C30B25/02 , C30B29/06 , H01L21/02381 , H01L21/02387 , H01L21/0243 , H01L21/02529 , H01L21/0262 , H01L21/02639 , H01L21/02658 , H01L29/66636 , H01L29/7848
摘要： A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped silicon film is also described. In the method, a substrate having a high polarity dielectric region and a low polarity crystalline region is provided. A precursor gas is flowed to provide a silyl surface above the high polarity dielectric region and a carbon-doped silicon layer above the low polarity crystalline region. The silyl surface is then removed from above the high polarity dielectric region. The flowing and removing steps are repeated to provide a carbon-doped silicon film of a desired thickness above the low polarity crystalline region.
摘要翻译：描述了用于沉积外延碳掺杂硅膜的前体气体混合物。前体气体混合物由体积的硅前体气体，一定体积的乙炔气体和一定体积的载气构成。还描述了形成具有外延碳掺杂硅膜的半导体结构的方法。在该方法中，提供具有高极性电介质区域和低极性结晶区域的衬底。流动前体气体以在高极性电介质区域上方提供甲硅烷基表面，以及在低极性结晶区域上方的碳掺杂硅层。然后从高极性介电区域上方除去甲硅烷基表面。重复流动和去除步骤以提供在低极性结晶区域之上所需厚度的碳掺杂硅膜。

7. 发明授权

US07682916B2 Field effect transistor structure with abrupt source/drain junctions 有权
标题翻译：具有突发的源极/漏极结的场效应晶体管结构
公开(公告)号：US07682916B2
公开(公告)日：2010-03-23
申请号：US12231172
申请日：2008-08-28
申请人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
发明人： Anand S. Murthy , Robert S. Chau , Patrick Morrow , Chia-Hong Jan , Paul Packan
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/02532 , H01L21/0262 , H01L21/2022 , H01L29/0646 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66477 , H01L29/66492 , H01L29/665 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/7834 , H01L29/7848
摘要： Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics. Alternative embodiments can be implemented with a back filled recess of a single conductivity type.
摘要翻译：体现本发明的微电子结构包括具有高导电性的源极/漏极延伸的场效应晶体管（FET）。形成这种高导电的源极/漏极延伸部分包括形成钝化的凹槽，其通过掺杂材料的外延沉积而填充以形成源极/漏极结。凹部包括在栅极结构的一部分下面的横向延伸的区域。这种横向延伸部可以位于与栅电极的垂直侧壁相邻的侧壁间隔物的下面，或者可以进一步延伸到FET的沟道部分中，使得侧向凹槽位于栅极结构的栅电极部分的下方。在一个实施例中，通过相对掺杂材料的双层的原位外延沉积来将凹部反向填充。以这种方式，实现了非常突然的结，其提供相对较低的电阻源极/漏极延伸并进一步提供良好的截止阈值泄漏特性。替代实施例可以用单导电类型的后填充凹槽来实现。

8. 发明授权

US07402872B2 Method for forming an integrated circuit 有权
标题翻译：集成电路形成方法
公开(公告)号：US07402872B2
公开(公告)日：2008-07-22
申请号：US11336160
申请日：2006-01-20
申请人： Anand S. Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Tahir Ghani
发明人： Anand S. Murthy , Glenn A. Glass , Andrew N. Westmeyer , Michael L. Hattendorf , Tahir Ghani
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7834 , H01L29/665 , H01L29/66636
摘要： A method is described for manufacturing an n-MOS semiconductor transistor. Recesses are formed in a semiconductor substrate adjacent a gate electrode structure. Silicon is embedded in the recesses via a selective epitaxial growth process. The epitaxial silicon is in-situ alloyed with substitutional carbon and in-situ doped with phosphorus. The silicon-carbon alloy generates a uniaxial tensile strain in the channel region between the source and drain, thereby increasing electron channel mobility and the transistor's drive current. The silicon-carbon alloy decreases external resistances by reducing contact resistance between source/drain and silicide regions and by reducing phosphorous diffusivity, thereby permitting closer placement of the transistor's source/drain and channel regions.
摘要翻译：描述了制造n-MOS半导体晶体管的方法。在与栅电极结构相邻的半导体衬底中形成凹部。硅通过选择性外延生长工艺嵌入凹槽中。外延硅与替代原位合金化并原位掺磷。硅碳合金在源极和漏极之间的沟道区域中产生单轴拉伸应变，从而增加电子通道迁移率和晶体管的驱动电流。硅碳合金通过降低源极/漏极和硅化物区域之间的接触电阻并且通过减少磷扩散性来降低外部电阻，从而允许晶体管的源极/漏极和沟道区域更接近地放置。

9. 发明申请

US20080135894A1 Transistor with improved tip profile and method of manufacture thereof 有权
标题翻译：具有改进尖端轮廓的晶体管及其制造方法
公开(公告)号：US20080135894A1
公开(公告)日：2008-06-12
申请号：US12009122
申请日：2008-01-15
申请人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
发明人： Mark T. Bohr , Steven J. Keating , Thomas A. Letson , Anand S. Murthy , Donald W. O'Neill , Willy Rachmady
IPC分类号： H01L29/94
CPC分类号： H01L29/045 , H01L21/30608 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.
摘要翻译：实施例是改进的晶体管结构和制造该结构的方法。特别地，实施例的湿蚀刻形成具有改进的尖端形状的源极和漏极区域，以通过改善短沟道效应的控制，增加饱和电流，改善冶金栅极长度的控制，增加载流子迁移率来提高晶体管的性能并且在源极和漏极与硅化物之间的界面处降低接触电阻。

10. 发明授权

US07060576B2 Epitaxially deposited source/drain 有权
标题翻译：外延沉积源/漏极
公开(公告)号：US07060576B2
公开(公告)日：2006-06-13
申请号：US10692696
申请日：2003-10-24
申请人： Nick Lindert , Anand S. Murthy , Justin K. Brask
发明人： Nick Lindert , Anand S. Murthy , Justin K. Brask
IPC分类号： H01L21/337 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/66628 , H01L29/66636
摘要： An epitaxially deposited source/drain extension may be formed for a metal oxide semiconductor field effect transistor. A sacrificial layer may be formed and etched away to undercut under the gate electrode. Then a source/drain extension of epitaxial silicon may be deposited to extend under the edges of the gate electrode. As a result, the extent by which the source/drain extension extends under the gate may be controlled by controlling the etching of the sacrificial material. Its thickness and depth may be controlled by controlling the deposition process. Moreover, the characteristics of the source/drain extension may be controlled independently of those of the subsequently formed deep or heavily doped source/drain junction.
摘要翻译：可以为金属氧化物半导体场效应晶体管形成外延沉积的源极/漏极延伸。可以形成牺牲层并蚀刻掉在栅电极下方的底切。然后，可以沉积外延硅的源极/漏极延伸部，以在栅电极的边缘下延伸。结果，可以通过控制牺牲材料的蚀刻来控制源极/漏极延伸在栅极下延伸的程度。其厚度和深度可以通过控制沉积过程来控制。此外，可以独立于后续形成的深度或重掺杂源极/漏极结的特性来控制源极/漏极延伸的特性。

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