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1. 发明申请

US20200098887A1 CONTACT ELECTRODES AND DIELECTRIC STRUCTURES FOR THIN FILM TRANSISTORS 审中-公开
公开(公告)号：US20200098887A1
公开(公告)日：2020-03-26
申请号：US16143326
申请日：2018-09-26
申请人： Gilbert DEWEY , Van H. LE , Abhishek SHARMA , Jack T. KAVALIEROS , Sean MA , Seung Hoon SUNG , Nazila HARATIPOUR , Tahir GHANI , Justin WEBER , Shriram SHIVARAMAN
发明人： Gilbert DEWEY , Van H. LE , Abhishek SHARMA , Jack T. KAVALIEROS , Sean MA , Seung Hoon SUNG , Nazila HARATIPOUR , Tahir GHANI , Justin WEBER , Shriram SHIVARAMAN
IPC分类号： H01L29/51 , H01L29/786 , H01L29/49 , H01L29/417 , H01L27/088 , H01L29/66
摘要： Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.

2. 发明授权

US09728464B2 Self-aligned 3-D epitaxial structures for MOS device fabrication 有权
公开(公告)号：US09728464B2
公开(公告)日：2017-08-08
申请号：US13560513
申请日：2012-07-27
申请人： Glenn A. Glass , Daniel B. Aubertine , Anand S. Murthy , Gaurav Thareja , Tahir Ghani
发明人： Glenn A. Glass , Daniel B. Aubertine , Anand S. Murthy , Gaurav Thareja , Tahir Ghani
IPC分类号： H01L21/335 , H01L21/8238 , H01L29/10
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L29/1054
摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

3. 发明申请

US20170047416A1 STRAINED GATE-ALL-AROUND SEMICONDUCTOR DEVICES FORMED ON GLOBALLY OR LOCALLY ISOLATED SUBSTRATES 审中-公开
标题翻译：在全球或当地分离的基底上形成的应变栅格全面的半导体器件
公开(公告)号：US20170047416A1
公开(公告)日：2017-02-16
申请号：US15335281
申请日：2016-10-26
申请人： Annalisa Cappellani , Abhijit Jayant Pethe , Tahir Ghani , Harry Gomez
发明人： Annalisa Cappellani , Abhijit Jayant Pethe , Tahir Ghani , Harry Gomez
IPC分类号： H01L29/423 , H01L29/786 , H01L29/06 , H01L29/78
CPC分类号： H01L29/42392 , B82Y10/00 , H01L21/30604 , H01L21/845 , H01L29/0649 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/41725 , H01L29/42356 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
摘要翻译：描述了形成在全局或局部隔离的基板上的应变门全面半导体器件。例如，半导体器件包括半导体衬底。绝缘结构设置在半导体衬底之上。三维沟道区设置在绝缘结构的上方。源极和漏极区域设置在三维沟道区域的两侧和外延晶种层上。外延种子层由不同于三维沟道区的半导体材料构成，并且设置在绝缘结构上。栅极电极堆叠围绕三维沟道区域，其中设置在绝缘结构上并且横向邻近外延籽晶层的部分。

4. 发明申请

US20170004998A1 GATE CONTACT STRUCTURE OVER ACTIVE GATE AND METHOD TO FABRICATE SAME 审中-公开
标题翻译：盖门接触结构和活动门的方法
公开(公告)号：US20170004998A1
公开(公告)日：2017-01-05
申请号：US15266819
申请日：2016-09-15
申请人： Abhijit Jayant Pethe , Tahir Ghani , Mark Bohr , Clair Webb , Harry Gomez , Annalisa Cappellani
发明人： Abhijit Jayant Pethe , Tahir Ghani , Mark Bohr , Clair Webb , Harry Gomez , Annalisa Cappellani
IPC分类号： H01L21/768 , H01L23/532 , H01L21/28 , H01L23/522 , H01L29/66 , H01L21/311
CPC分类号： H01L21/76897 , H01L21/28008 , H01L21/31111 , H01L21/76807 , H01L21/76834 , H01L21/76895 , H01L23/5226 , H01L23/53257 , H01L29/66545 , H01L29/66583 , H01L29/785
摘要： Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
摘要翻译：描述了设置在门的有效部分上的栅极接触结构以及形成这种栅极接触结构的方法。例如，半导体结构包括具有有源区和隔离区的衬底。栅极结构具有设置在有源区上方的部分和设置在衬底的隔离区上方的部分。源极和漏极区域设置在衬底的有源区域中，位于栅极结构的位于有源区域之上的部分的任一侧上。栅极接触结构设置在栅极结构的设置在衬底的有源区上方的部分上。

5. 发明申请

US20150171218A1 MULTI-THRESHOLD VOLTAGE DEVICES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS 有权
标题翻译：多电压电压器件及相关技术及配置
公开(公告)号：US20150171218A1
公开(公告)日：2015-06-18
申请号：US14108265
申请日：2013-12-16
申请人： Joseph M. Steigerwald , Tahir Ghani , Jenny Hu , Ian R. C. Post
发明人： Joseph M. Steigerwald , Tahir Ghani , Jenny Hu , Ian R. C. Post
IPC分类号： H01L29/78 , H01L29/423 , H01L21/28 , H01L29/66
CPC分类号： H01L29/7831 , H01L21/28114 , H01L21/823431 , H01L21/82345 , H01L21/823456 , H01L27/0886 , H01L29/42372 , H01L29/42376 , H01L29/4908 , H01L29/4958 , H01L29/4966 , H01L29/517 , H01L29/66484 , H01L29/66772 , H01L29/66795 , H01L29/7855 , H01L29/7856 , H01L29/78645
摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了多阈值电压装置及相关联的技术和配置。在一个实施例中，一种装置包括半导体衬底，设置在半导体衬底上的沟道体，具有与沟道本体耦合的第一厚度的第一栅电极和具有与沟道本体耦合的第二厚度的第二栅电极，其中，第一厚度大于第二厚度。可以描述和/或要求保护其他实施例。

6. 发明申请

US20140264679A1 LOGIC CHIP INCLUDING EMBEDDED MAGNETIC TUNNEL JUNCTIONS 有权
标题翻译：逻辑芯片，包括嵌入式磁性隧道结
公开(公告)号：US20140264679A1
公开(公告)日：2014-09-18
申请号：US13994716
申请日：2013-03-15
申请人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
发明人： Kevin J. Lee , Tahir Ghani , Joseph M. Steigerwald , John H. Epple , Yih Wang
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： H01L43/12 , G11C11/161 , H01L27/222 , H01L27/226 , H01L43/08
摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.
摘要翻译：实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上部MTJ层，较低MTJ层和直接接触上层MTJ层和下层MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。在一个实施例中，第一和第二ILD直接彼此接触。本文描述了其它实施例。

7. 发明申请

US20140191300A1 HARD MASK ETCH STOP FOR TALL FINS 有权
标题翻译：硬盘防火墙防火墙
公开(公告)号：US20140191300A1
公开(公告)日：2014-07-10
申请号：US13997161
申请日：2011-12-31
申请人： Ritesh Jhaveri , Bernard Sell , Tahir Ghani
发明人： Ritesh Jhaveri , Bernard Sell , Tahir Ghani
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/0638 , H01L21/823431 , H01L21/823821 , H01L29/0649 , H01L29/66795 , H01L29/785
摘要： A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.
摘要翻译：在高鳍的顶表面上形成硬掩模蚀刻停止件以保持翅片高度，并且在晶体管制造工艺的蚀刻步骤期间保护翅片的顶表面免受损坏。在一个实施例中，使用双硬掩模系统形成硬掩模蚀刻停止件，其中在衬底的表面上形成硬掩模蚀刻停止层，并且使用第二硬掩模层来用硬掩模在鳍的顶表面上的蚀刻停止层。去除第二硬掩模层，同时保留硬掩模蚀刻停止层以在随后的制造步骤期间保护翅片的顶表面。

8. 发明授权

US08735869B2 Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates 有权
标题翻译：形成在全局或局部隔离的基板上的应变门全面半导体器件
公开(公告)号：US08735869B2
公开(公告)日：2014-05-27
申请号：US13629135
申请日：2012-09-27
申请人： Annalisa Cappellani , Abhijit Jayant Pethe , Tahir Ghani , Harry Gomez
发明人： Annalisa Cappellani , Abhijit Jayant Pethe , Tahir Ghani , Harry Gomez
IPC分类号： H01L29/06
CPC分类号： H01L29/42392 , B82Y10/00 , H01L21/30604 , H01L21/845 , H01L29/0649 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/41725 , H01L29/42356 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
摘要翻译：描述了形成在全局或局部隔离的基板上的应变门全面半导体器件。例如，半导体器件包括半导体衬底。绝缘结构设置在半导体衬底之上。三维沟道区设置在绝缘结构的上方。源极和漏极区域设置在三维沟道区域的两侧和外延晶种层上。外延种子层由不同于三维沟道区的半导体材料构成，并且设置在绝缘结构上。栅极电极堆叠围绕三维沟道区域，其中设置在绝缘结构上并且横向邻近外延籽晶层的部分。

9. 发明申请

US20130285155A1 III-V LAYERS FOR N-TYPE AND P-TYPE MOS SOURCE-DRAIN CONTACTS 有权
标题翻译：用于N型和P型MOS源 - 漏联系的III-V层
公开(公告)号：US20130285155A1
公开(公告)日：2013-10-31
申请号：US13976074
申请日：2011-12-20
申请人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
发明人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
IPC分类号： H01L27/092
CPC分类号： H01L29/78618 , H01L21/76805 , H01L21/76886 , H01L21/76895 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L21/823871 , H01L27/092 , H01L27/0924 , H01L29/0669 , H01L29/0673 , H01L29/0847 , H01L29/1037 , H01L29/267 , H01L29/41791 , H01L29/42392 , H01L29/66545 , H01L29/78 , H01L29/78654 , H01L29/78684 , H01L29/78696
摘要： Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.
摘要翻译：公开了用于形成相对于常规器件具有降低的寄生接触电阻的晶体管器件的技术。在一些示例性实施例中，该技术可以用于实现CMOS器件的MOS晶体管的触点，其中在p型和n型源极/漏极区之间提供中间III-V半导体材料层及其各自的触点金属显着降低接触电阻。中间III-V半导体材料层可以具有小的带隙（例如，低于0.5eV）和/或以其它方式被掺杂以提供期望的导电性。这些技术可以用于许多晶体管架构（例如，平面，鳍状和纳米线晶体管），包括应变和无约束通道结构。

10. 发明申请

US20130277752A1 SELF-ALIGNED CONTACT METALLIZATION FOR REDUCED CONTACT RESISTANCE 有权
公开(公告)号：US20130277752A1
公开(公告)日：2013-10-24
申请号：US13976075
申请日：2011-12-20
申请人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
发明人： Glenn A. Glass , Anand S. Murthy , Tahir Ghani
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/0922 , H01L21/28185 , H01L21/28525 , H01L21/28575 , H01L21/76814 , H01L21/823814 , H01L21/823821 , H01L21/8258 , H01L23/535 , H01L27/0605 , H01L27/0924 , H01L29/0669 , H01L29/0847 , H01L29/16 , H01L29/165 , H01L29/20 , H01L29/267 , H01L29/41725 , H01L29/41783 , H01L29/41791 , H01L29/42392 , H01L29/517 , H01L29/66545 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g.,

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