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1. 发明申请

US20090097320A1 Memory Cells, Electronic Systems, Methods Of Forming Memory Cells, And Methods of Programming Memory Cells 有权
标题翻译：记忆单元，电子系统，形成记忆单元的方法，以及编程记忆单元的方法
公开(公告)号：US20090097320A1
公开(公告)日：2009-04-16
申请号：US11871339
申请日：2007-10-12
申请人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
发明人： Kyu S. Min , Rhett T. Brewer , Tejas Krishnamohan , Thomas M. Graettinger , D. V. Ramaswamy , Ronald A. Weimer , Arup Bhattacharyya
IPC分类号： G11C16/04 , H01L29/792
CPC分类号： G11C16/0483 , B82Y10/00 , G11C11/5671 , G11C16/0475 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/42348 , Y10S977/943
摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.
摘要翻译：一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。电介质材料可以包括高k材料。一个或多个电荷捕获区可以包括金属材料。这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。一些实施例包括包括存储器单元的电子系统。一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

2. 发明申请

US20070048946A1 Transistor gate forming methods and integrated circuits 有权
标题翻译：晶体管栅极形成方法和集成电路
公开(公告)号：US20070048946A1
公开(公告)日：2007-03-01
申请号：US11219079
申请日：2005-09-01
申请人： D. V. Ramaswamy , Ravi Iyer
发明人： D. V. Ramaswamy , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L21/28088 , H01L21/823842 , H01L29/78
摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
摘要翻译：晶体管栅极形成方法包括形成第一和第二晶体管栅极。两个栅极中的每一个包括下金属层和上金属层。第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现的功函数相同的功函数的沉积材料。然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现的功函数不同的修正功函数。与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

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