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1. 发明申请

US20070048946A1 Transistor gate forming methods and integrated circuits 有权
标题翻译：晶体管栅极形成方法和集成电路
公开(公告)号：US20070048946A1
公开(公告)日：2007-03-01
申请号：US11219079
申请日：2005-09-01
申请人： D. V. Ramaswamy , Ravi Iyer
发明人： D. V. Ramaswamy , Ravi Iyer
IPC分类号： H01L21/336
CPC分类号： H01L21/28088 , H01L21/823842 , H01L29/78
摘要： A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.
摘要翻译：晶体管栅极形成方法包括形成第一和第二晶体管栅极。两个栅极中的每一个包括下金属层和上金属层。第一栅极的下金属层源自表现出与第二栅极的下金属层源自的沉积材料所表现的功函数相同的功函数的沉积材料。然而，第一栅极的下部金属层表现出与第二栅极的下部金属层所表现的功函数不同的修正功函数。与第二栅极的下金属层相比，第一栅极的下金属层可以含有较少的氧和/或碳。与第二栅极的下金属层相比，第一栅极的下金属层可以含有更多的氮。第一栅极可以是n沟道栅极，第二栅极可以是p沟道栅极。

2. 发明授权

US09076888B2 Silicided recessed silicon 有权
公开(公告)号：US09076888B2
公开(公告)日：2015-07-07
申请号：US11614802
申请日：2006-12-21
申请人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas A. Figura , Gordon A. Haller , Ravi Iyer , John Mark Meldrim , Justin Harnish
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L21/8238 , H01L21/28 , H01L21/8234 , H01L27/108 , H01L29/49 , H01L29/66
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.

3. 发明申请

US20140019736A1 Embedded Branch Prediction Unit 有权
标题翻译：嵌入式分支预测单元
公开(公告)号：US20140019736A1
公开(公告)日：2014-01-16
申请号：US13992723
申请日：2011-12-30
申请人： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
发明人： Xiaowei Jiang , Srihari Makineni , Zhen Fang , Dmitri Pavlov , Ravi Iyer
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30058
摘要： In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the instruction fetch unit instead of the decode stage. In addition, the branch prediction unit may include no branch predictor. Also, the return address stack may be associated with the instruction decode stage and is structurally separate from the branch prediction unit. In some cases, this arrangement reduces the area of the branch prediction unit, as well as power consumption.
摘要翻译：根据本发明的一些实施例，用于嵌入式控制器的分支预测单元可以与指令提取单元相关联而不是解码级放置。另外，分支预测单元也可以不包括分支预测器。此外，返回地址堆栈可以与指令解码级相关联，并且在结构上与分支预测单元分离。在某些情况下，这种布置减少了分支预测单元的面积以及功耗。

4. 发明授权

US07659560B2 Transistor structures 有权
标题翻译：晶体管结构
公开(公告)号：US07659560B2
公开(公告)日：2010-02-09
申请号：US11716433
申请日：2007-03-08
申请人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
发明人： Sanh D. Tang , Gordon A. Haller , Prashant Raghu , Ravi Iyer
IPC分类号： H01L21/8238
CPC分类号： H01L29/78696 , H01L29/42392 , H01L29/66787
摘要： A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures.
摘要翻译：晶体管栅极形成方法包括在线路开口内形成金属层，并在金属层的开口内形成填充层。填充层相对于金属层基本上可选择性地蚀刻。晶体管结构包括线路开口，开口内的电介质层，开口内的电介质层上的金属层，以及开口内的金属层上的填充层。如果填充层被金属层的增加的厚度代替，则金属层/填充层组合的内在特性小于否则会存在。本发明至少应用于三维晶体管结构。

5. 发明申请

US20100020819A1 Packet coalescing 有权
标题翻译：分组聚合
公开(公告)号：US20100020819A1
公开(公告)日：2010-01-28
申请号：US12586964
申请日：2009-09-30
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04L12/66
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

6. 发明授权

US07294893B2 Titanium silicide boride gate electrode 有权
标题翻译：硅化钛硼化物栅电极
公开(公告)号：US07294893B2
公开(公告)日：2007-11-13
申请号：US10926871
申请日：2004-08-26
申请人： Ravi Iyer
发明人： Ravi Iyer
IPC分类号： H01L29/76
CPC分类号： H01L29/4941 , H01L21/28061 , H01L21/76895
摘要： A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.
摘要翻译：用于制造栅电极的方法包括提供栅极氧化层并在氧化物层上形成硼化钛层。在硼化钛层上形成绝缘体盖层，之后，由硼化钛层形成栅电极。在形成硼化钛层之前，可以在氧化物层上形成阻挡层，其中栅电极由阻挡层和硼化钛层形成。此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层，其中栅电极由硼化钛层和多晶硅层形成。此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层和在多晶硅层上形成的势垒层。然后，由多晶硅层，阻挡层和硼化钛层形成栅电极。类似的方法可以进一步用于形成互连以连接接触区域。还描述了由该方法产生的栅电极结构和互连结构。此外，在这些方法和结构中，硼化钛层可以是二硼化钛层或其中掺入硅的硼化钛层。

7. 发明授权

US07268078B2 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants 失效
标题翻译：来自四氯化钛和烃反应物的钛的化学气相沉积
公开(公告)号：US07268078B2
公开(公告)日：2007-09-11
申请号：US11298978
申请日：2005-12-09
申请人： Ravi Iyer , Sujit Sharan
发明人： Ravi Iyer , Sujit Sharan
IPC分类号： H01L21/44
CPC分类号： C23C16/08 , H01L21/28556 , H01L21/28568 , Y10S438/909
摘要： A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.
摘要翻译：公开了一种通过化学气相沉积沉积钛金属层的工艺。该方法即使在具有大于1:5的纵横比的沟槽和接触开口中也提供具有高度保形性的沉积钛层。

8. 发明申请

US20070049015A1 Silicided recessed silicon 有权
标题翻译：硅胶凹槽硅
公开(公告)号：US20070049015A1
公开(公告)日：2007-03-01
申请号：US11219303
申请日：2005-09-01
申请人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
发明人： Hasan Nejad , Thomas Figura , Gordon Haller , Ravi Iyer , John Meldrim , Justin Harnish
IPC分类号： H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823418 , H01L21/823443 , H01L21/823814 , H01L27/10852 , H01L27/10876 , H01L27/10897 , H01L29/4975 , H01L29/66621 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays.
摘要翻译：为嵌入硅完全硅化提供了方法和结构。在沟槽内提供硅。在硅上提供了一种金属混合物，其中一种金属在硅中比硅中更容易扩散到金属中，而另一种金属在硅中比在金属中的硅更容易扩散。示例性的混合物包括80％的镍和20％的钴。尽管沟槽的纵横比相对较高，但沟槽内的硅可以完全无硅化物形成。在其他设备中，可以通过用于存储器阵列的方法形成凹陷接入设备（RAD）。

9. 发明授权

US07115492B2 Technique for elimination of pitting on silicon substrate during gate stack etch using material in a non-annealed state 有权
标题翻译：使用非退火状态的材料进行栅叠层蚀刻时消除硅衬底上点蚀的技术
公开(公告)号：US07115492B2
公开(公告)日：2006-10-03
申请号：US10630268
申请日：2003-07-30
申请人： Pai-Hung Pan , Louie Liu , Ravi Iyer
发明人： Pai-Hung Pan , Louie Liu , Ravi Iyer
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28052
摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.
摘要翻译：一种用于形成栅堆叠的方法，其通过在形成期间的温度降低来最小化或消除在栅叠层形成期间对栅介质层和/或硅衬底的损坏。温度降低防止在栅极堆叠中的金属硅化物膜内形成硅团簇，这已被发现在栅极蚀刻步骤期间造成损坏。本发明还包括在栅极蚀刻步骤之前分散硅簇的方法。

10. 发明申请

US20060134912A1 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants 失效
标题翻译：来自四氯化钛和烃反应物的钛的化学气相沉积
公开(公告)号：US20060134912A1
公开(公告)日：2006-06-22
申请号：US11298978
申请日：2005-12-09
申请人： Ravi Iyer , Sujit Sharan
发明人： Ravi Iyer , Sujit Sharan
IPC分类号： H01L21/44
CPC分类号： C23C16/08 , H01L21/28556 , H01L21/28568 , Y10S438/909
摘要： A process for depositing titanium metal layers via chemical vapor deposition is disclosed. The process provides deposited titanium layers having a high degree of conformality, even in trenches and contact openings having aspect ratios greater than 1:5.
摘要翻译：公开了一种通过化学气相沉积沉积钛金属层的工艺。该方法即使在具有大于1:5的纵横比的沟槽和接触开口中也提供具有高度保形性的沉积钛层。

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