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1. 发明授权

US08964555B1 Data network with constrained switch transmission rates 有权
标题翻译：具有受限切换传输速率的数据网络
公开(公告)号：US08964555B1
公开(公告)日：2015-02-24
申请号：US13533265
申请日：2012-06-26
申请人： David A. Miller
发明人： David A. Miller
IPC分类号： H04L12/815
CPC分类号： H04L12/40136 , H04L47/13 , H04L47/22 , H04L2012/4028 , Y02D50/10
摘要： A data network includes a plurality of end systems; a plurality of line data buses connected to the end systems; and a plurality of switches connected to the line data buses and to other switches via trunk data buses to define a star topology. The switches and end systems are configured to operate asynchronously. Each switch includes a number of packet schedulers for managing the transmission of received data flow. A number of effective line rate utilization mechanisms are each associated with a respective packet scheduler for providing the service rate of that packet scheduler. Switch egress ports transmit the received data flow. Each switch egress port has a defined configured effective transmission rate. Each effective line rate utilization mechanism reduces the utilization rate to the defined configured effective transmission rate.
摘要翻译：数据网络包括多个终端系统; 连接到端系统的多条线数据总线; 以及多个开关，其通过中继线数据总线连接到线路数据总线和其它交换机，以定义星形拓扑。交换机和终端系统被配置为异步运行。每个交换机包括用于管理接收的数据流的传输的多个分组调度器。多个有效的线路利用率机制各自与相应的分组调度器相关联，用于提供该分组调度器的服务速率。交换出口端口发送接收到的数据流。每个交换机出口端口具有定义的配置的有效传输速率。每个有效的线路利用率机制将利用率降低到规定的有效传输速率。

2. 发明授权

US08958297B1 Data network with “per flow” flow monitoring 有权
标题翻译：数据网络采用“每流”流量监控
公开(公告)号：US08958297B1
公开(公告)日：2015-02-17
申请号：US13533572
申请日：2012-06-26
申请人： David A. Miller , Daniel E. Mazuk
发明人： David A. Miller , Daniel E. Mazuk
IPC分类号： H04L12/815
CPC分类号： H04L47/564 , H04L47/215 , H04L47/22 , H04L49/3018
摘要： A ‘per flow’ flow monitor is operatively associated with each ingress port of the switch of the data network, for monitoring the arrival data flow on each flow in defined traffic constraint envelopes containing frames. An eligibility time computation mechanism computes an eligibility time at which arriving frames on each flow will be conformant to the defined traffic envelope to the ingress port given past frame arrivals on that same flow. A holding mechanism holds the arriving frames on each flow until the eligibility time is reached. A release mechanism releases the arriving frames on a flow at the eligibility time. The flow monitor, computation mechanism, holding mechanism, and release mechanism cooperate to provide an ‘per flow’ traffic shaping function in conformance with delay and delay-jitter bound, frame loss probability, and bandwidth provisioning requirements, thus allowing the switch to enforce the traffic constraint envelope for each flow.
摘要翻译： “每流”流量监视器与数据网络的交换机的每个入口端口可操作地相关联，用于监视包含帧的定义的业务约束包络中的每个流的到达数据流。资格时间计算机制计算出每个流程上的到达帧将符合定义的流量包络的资格时间，以确定给定过去帧流到同一流程的入口端口。保持机构将到达的帧保持在每个流程上，直到达到资格时间。释放机制在合格时间内将流动的框架释放。流量监测器，计算机制，保持机制和释放机制协同提供符合延迟抖动约束，帧丢失概率和带宽配置要求的“每流”流量整形功能，从而允许交换机强制执行每个流量的流量约束包络。

3. 发明授权

US08078055B1 Passive optical avionics network 有权
标题翻译：被动光电航空网络
公开(公告)号：US08078055B1
公开(公告)日：2011-12-13
申请号：US12151249
申请日：2008-05-05
申请人： Daniel E. Mazuk , Peter J. Morgan , David A. Miller , Nicholas H. Bloom , Mark A. Kovalan
发明人： Daniel E. Mazuk , Peter J. Morgan , David A. Miller , Nicholas H. Bloom , Mark A. Kovalan
IPC分类号： H04B10/20
CPC分类号： H04B10/272
摘要： The present disclosure is directed to a passive optical avionics network system and method.A passive avionics network may comprise: (a) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the OLT and the ONU; and (d) an avionics module operably coupled to the ONU.An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the LRU and the ONU; and (d) an avionics module operably coupled to the ONU.A method for avionics network communication may comprise: (a) providing avionics data; (b) transmitting the avionics data via a fiber optic network; (c) receiving the avionics data; and (d) controlling functionality of an avionics module according to the avionics data.
摘要翻译：本公开涉及无源光学航空电子网络系统和方法。被动航空电子网络可以包括：（a）光线路终端（OLT）; （b）至少一个光网络单元（ONU）; （c）可操作地耦合OLT和ONU的光纤总线; 和（d）可操作地耦合到所述ONU的航空电子模块。集成模块化航空电子（IMA）系统可以包括：（a）线路可替换单元（LRU），所述LRU包括：（i）处理单元; 和（ii）光线路终端（OLT）; （b）至少一个光网络单元（ONU）; （c）可操作地耦合LRU和ONU的光纤总线; 和（d）可操作地耦合到所述ONU的航空电子模块。航空电子网络通信的方法可以包括：（a）提供航空电子数据; （b）通过光纤网络发送航空电子数据; （c）接收航空电子数据; 以及（d）根据航空电子数据来控制航空电子模块的功能。

4. 外观设计

USD645541S1 Paint sprayer 有权
标题翻译：油漆喷雾器
公开(公告)号：USD645541S1
公开(公告)日：2011-09-20
申请号：US29388137
申请日：2011-03-24
申请人： David A. Miller
设计人： David A. Miller

5. 外观设计

USD595162S1 Non-contact thermometer 有权
标题翻译：非接触式温度计
公开(公告)号：USD595162S1
公开(公告)日：2009-06-30
申请号：US29328885
申请日：2008-12-03
申请人： Christopher J. Murray , Michael L. Agronin , David A. Miller
设计人： Christopher J. Murray , Michael L. Agronin , David A. Miller

6. 外观设计

USD593827S1 Drill 有权
公开(公告)号：USD593827S1
公开(公告)日：2009-06-09
申请号：US29329460
申请日：2008-12-16
申请人： David A. Miller , Weston J. Van Wambeke
设计人： David A. Miller , Weston J. Van Wambeke

7. 发明授权

US06842644B2 User navigation and guidance during configuration and storage of parameters for medical device 失效
标题翻译：用于医疗设备参数配置和存储期间的导航和指导
公开(公告)号：US06842644B2
公开(公告)日：2005-01-11
申请号：US10008525
申请日：2001-11-02
申请人： Thomas N. Anderson , John D. Higinbotham , David A. Miller , Mark Schwartz , C. Denise Thompson
发明人： Thomas N. Anderson , John D. Higinbotham , David A. Miller , Mark Schwartz , C. Denise Thompson
IPC分类号： A61N1/372 , A61N1/37
CPC分类号： A61N1/37235
摘要： Systems and methods for providing a navigation and guidance sequence during configuration, input, and storage of programmable parameters for use in a medical device. One embodiment includes a cardiac rhythm management device as the medical device. The navigational sequence provides a series of interfaces on which parameter input fields are displayed. In one embodiment, the interfaces are graphical user interfaces. Each interface may include a plurality of different sets of parameter input fields with only one set being displayed at a time.
摘要翻译：用于在用于医疗设备的可编程参数的配置，输入和存储期间提供导航和指导序列的系统和方法。一个实施例包括作为医疗装置的心律管理装置。导航序列提供了一系列接口，其中显示参数输入字段。在一个实施例中，接口是图形用户界面。每个接口可以包括多个不同的参数输入区域集合，一次只显示一个集合。

8. 发明授权

US06463529B1 Processor based system with system wide reset and partial system reset capabilities 失效
标题翻译：基于处理器的系统具有系统复位和部分系统复位功能
公开(公告)号：US06463529B1
公开(公告)日：2002-10-08
申请号：US08797036
申请日：1997-02-10
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley
IPC分类号： G06F124
CPC分类号： G06F12/0802 , G06F1/24 , G06F15/177
摘要： A processor-based system includes a processing unit. The processing unit includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. The processing unit is reset in response to a system reset signal being asserted at a reset input node and only selected portions of the processing unit are reset in response to a partial-reset signal being asserted at a partial-reset input node. The system can also include a number of other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.
摘要翻译：基于处理器的系统包括处理单元。处理单元至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。处理单元响应于在复位输入节点断言的系统复位信号被复位，并且响应于部分复位输入节点断言的部分复位信号仅复位处理单元的选定部分。该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

9. 发明授权

US06314515B1 Resetting multiple processors in a computer system 失效
标题翻译：在计算机系统中重置多个处理器
公开(公告)号：US06314515B1
公开(公告)日：2001-11-06
申请号：US09356472
申请日：1999-07-19
申请人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
发明人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
IPC分类号： G06F15177
CPC分类号： G06F11/1417 , G06F9/4403 , G06F9/4405 , G06F9/4416 , G06F11/2038 , G06F11/2043 , G06F11/22 , G06F11/2284 , G06F15/177
摘要： Two design variations which allow multiple processors to start up using a single ROM are disclosed. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
摘要翻译：公开了允许使用单个ROM启动多个处理器的两种设计变型。在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。第一种技术适用于一般的多处理器系统，因为这种设计的实现可以从外部软件运行，也可以从添加到正在使用它的特定机器的操作系统运行。第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

10. 发明授权

US5497497A Method and apparatus for resetting multiple processors using a common ROM 失效
标题翻译：使用公共ROM复位多个处理器的方法和装置
公开(公告)号：US5497497A
公开(公告)日：1996-03-05
申请号：US51601
申请日：1993-04-22
申请人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
发明人： David A. Miller , Kenneth A. Jansen , Montgomery C. McGraw , Darren J. Cepulis
IPC分类号： G06F9/445 , G06F11/14 , G06F11/20 , G06F11/22 , G06F9/40 , G06F9/42 , G06F11/34
CPC分类号： G06F11/1417 , G06F11/22 , G06F11/2284 , G06F15/177 , G06F9/4403 , G06F9/4405 , G06F11/2038 , G06F11/2043 , G06F9/4416
摘要： Two design variations which allow multiple processors to start up using a single ROM. In each design, a single, primary processor is allowed to perform a complete POST while the remaining, secondary processors are directed in the course of their POST to perform a more limited initialization sequence. At power on, the primary processor begins a normal POST, while the secondary processors are held until a vector is placed into a redirection vector location. Each secondary processor is then subsequently started, using its own initialization code located at the address indicated by the redirection vector. The first technique is applicable to general multiprocessor systems because the implementation of this design can be run either from external software or from an addition to the operating system of the particular machine on which it is being used. The second technique is more specifically oriented to a particular system, and includes the use of an identity register to differentiate between primary and secondary processors.
摘要翻译：两种设计变化，允许多个处理器使用单个ROM启动。在每个设计中，允许单个主处理器执行完整的POST，而剩余的辅助处理器在其POST过程中被引导以执行更有限的初始化序列。上电时，主处理器开始正常POST，而辅助处理器保持，直到向量放置到重定向向量位置。然后，使用其位于由重定向向量指示的地址处的自己的初始化代码随后启动每个二级处理器。第一种技术适用于一般的多处理器系统，因为这种设计的实现可以从外部软件运行，也可以从添加到正在使用它的特定机器的操作系统运行。第二种技术更具体地针对特定系统，并且包括使用身份寄存器来区分主处理器和辅助处理器。

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