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1. 发明授权

US08205016B2 Controller receiving a configuration command while receiving an auxiliary supply voltage 有权
标题翻译：控制器在接收辅助电源电压的同时接收配置命令
公开(公告)号：US08205016B2
公开(公告)日：2012-06-19
申请号：US13046339
申请日：2011-03-11
申请人： Kevin B. Leigh , Paul R. Culley , Kevin G. Depew , Andrew Brown , Daniel N. Cripe , Jeffrey R. Hilland
发明人： Kevin B. Leigh , Paul R. Culley , Kevin G. Depew , Andrew Brown , Daniel N. Cripe , Jeffrey R. Hilland
IPC分类号： G06F3/00
CPC分类号： G06F9/4411
摘要： In at least some embodiments, a system comprises a plurality of electrical devices and management logic coupled to the electrical devices. While the electrical devices are each in a pre-boot environment, the management logic obtains information from the electrical devices and uses the information to determine electrical compatibility of, and/or configure, the electrical devices.
摘要翻译：在至少一些实施例中，系统包括耦合到电气设备的多个电气设备和管理逻辑。虽然电气设备都处于预引导环境中，但是管理逻辑从电气设备获得信息并且使用该信息来确定电气设备的电气兼容性和/或配置电气设备。

2. 发明授权

US07930440B2 Determining electrical compatibility and/or configuration of devices in a pre-boot environment 有权
标题翻译：确定预引导环境中设备的电气兼容性和/或配置
公开(公告)号：US07930440B2
公开(公告)日：2011-04-19
申请号：US11669912
申请日：2007-01-31
申请人： Kevin B. Leigh , Paul R. Culley , Kevin G. Depew , Andrew Brown , Daniel N. Cripe , Jeffrey R. Hilland
发明人： Kevin B. Leigh , Paul R. Culley , Kevin G. Depew , Andrew Brown , Daniel N. Cripe , Jeffrey R. Hilland
IPC分类号： G06F3/00
CPC分类号： G06F9/4411
摘要： In at least some embodiments, a system comprises a plurality of electrical devices and management logic coupled to the electrical devices. While the electrical devices are each in a pre-boot environment, the management logic obtains information from the electrical devices and uses the information to determine electrical compatibility of, and/or configure, the electrical devices.
摘要翻译：在至少一些实施例中，系统包括耦合到电气设备的多个电气设备和管理逻辑。虽然电气设备都处于预引导环境中，但是管理逻辑从电气设备获得信息并且使用该信息来确定电气设备的电气兼容性和/或配置电气设备。

3. 发明授权

US07565504B2 Memory window access mechanism 有权
标题翻译：内存窗口访问机制
公开(公告)号：US07565504B2
公开(公告)日：2009-07-21
申请号：US10401234
申请日：2003-03-27
申请人： David J. Garcia , Jeffrey R. Hilland , Paul R. Culley
发明人： David J. Garcia , Jeffrey R. Hilland , Paul R. Culley
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F12/1458
摘要： The disclosed embodiments may relate to memory window access, which may include a memory window and protection domain associated with a process. The memory window access setting or bit may also allow a plurality of memory windows to be associated with a protection domain for a process. The memory window access setting or bit may allow access to the memory window to be for the queue pairs in a certain protection domain or a designated queue pair.
摘要翻译：所公开的实施例可以涉及存储器窗口访问，其可以包括与进程相关联的存储器窗口和保护域。存储器窗口访问设置或位还可以允许多个存储器窗口与进程的保护域相关联。存储器窗口访问设置或位可以允许访问存储器窗口以用于特定保护域或指定队列对中的队列对。

4. 发明申请

US20080312888A1 Method for determining cooling requirements of a computer system enclosure 有权
标题翻译：确定计算机系统外壳的冷却要求的方法
公开(公告)号：US20080312888A1
公开(公告)日：2008-12-18
申请号：US12213146
申请日：2008-06-16
申请人： Wade D. Vinson , Paul R. Culley , Thomas D. Rhodes
发明人： Wade D. Vinson , Paul R. Culley , Thomas D. Rhodes
IPC分类号： G06F17/10
CPC分类号： G06F1/20
摘要： A computer-implemented method is used for determining cooling requirements of a computer system enclosure, where the enclosure includes a number of installed modules, the modules including fan modules. The method includes the steps of determining an individual impedance curve of each installed module; determining fan curves for the installed fan modules; based on the individual impedance curves, determining an overall system impedance curve for the computer system; determining desired performance requirements for the computer system; based on the desired performance requirements, determining corresponding fan curves; and choosing a fan curve that intersects the system impedance curve.
摘要翻译：计算机实现的方法用于确定计算机系统机箱的冷却需求，其中机箱包括多个已安装的模块，模块包括风扇模块。该方法包括以下步骤：确定每个安装的模块的单个阻抗曲线; 确定安装的风扇模块的风扇曲线; 基于各个阻抗曲线，确定计算机系统的整个系统阻抗曲线; 确定计算机系统的期望性能要求; 根据所需的性能要求，确定相应的风扇曲线; 并选择与系统阻抗曲线相交的风扇曲线。

5. 发明申请

US20080276082A1 COMPARING CHRACTERISTICS PRIOR TO BOOTING DEVICES 有权
标题翻译：比较装置前的比较
公开(公告)号：US20080276082A1
公开(公告)日：2008-11-06
申请号：US11742594
申请日：2007-05-01
申请人： Paul R. Culley , Kevin B. Leigh
发明人： Paul R. Culley , Kevin B. Leigh
IPC分类号： G06F15/177
CPC分类号： G06F1/26 , G06F1/189
摘要： A system that comprises a first electronic device comprising a non-volatile memory. The system also comprises another electronic device in communication with the first electronic device and comprising a second non-volatile memory. The system further comprises a control logic coupled to the first and second electronic devices. Each of the non-volatile memories stores electrical characteristics associated with a corresponding electronic device. Prior to booting up the first or second electronic device, the control logic obtains and compares at least some of the electrical characteristics and disables the communication as a result of the comparison.
摘要翻译：一种包括包括非易失性存储器的第一电子设备的系统。该系统还包括与第一电子设备通信并且包括第二非易失性存储器的另一电子设备。该系统还包括耦合到第一和第二电子设备的控制逻辑。每个非易失性存储器存储与相应的电子设备相关联的电特性。在引导第一或第二电子设备之前，控制逻辑获得并比较至少一些电气特性，并且作为比较的结果来禁止通信。

6. 发明授权

US5870602A Multi-processor system with system wide reset and partial system reset capabilities 失效
标题翻译：具有系统复位和部分系统复位功能的多处理器系统
公开(公告)号：US5870602A
公开(公告)日：1999-02-09
申请号：US14369
申请日：1998-01-27
申请人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
发明人： David A. Miller , Kenneth A. Jansen , Paul R. Culley , Mark Taylor , Javier F. Izquierdo
IPC分类号： G06F1/24 , G06F9/00
CPC分类号： G06F1/24
摘要： A multiprocessor system includes first and second processing units. Each of these processing units includes at least a processor and preferably also a cache memory, a cache memory controller and a numerical coprocessor. Each processing unit is reset in response to a system reset signal but only selected portions of the processing units are reset in response to a partial-reset signal. The system can also include a number other components such as video circuitry, a hard disk drive, bus interface circuitry, a speaker, a keyboard controller and a keyboard.
摘要翻译：多处理器系统包括第一和第二处理单元。这些处理单元中的每一个至少包括处理器，优选地还包括高速缓冲存储器，高速缓冲存储器控制器和数字协处理器。每个处理单元响应于系统复位信号被复位，但只响应于部分复位信号来复位处理单元的选定部分。该系统还可以包括许多其他组件，例如视频电路，硬盘驱动器，总线接口电路，扬声器，键盘控制器和键盘。

7. 发明授权

US5822571A Synchronizing data between devices 失效
标题翻译：在设备之间同步数据
公开(公告)号：US5822571A
公开(公告)日：1998-10-13
申请号：US659142
申请日：1996-06-05
申请人： Alan L. Goodrum , Jens K. Ramsey , Paul R. Culley , Joseph P. Miller
发明人： Alan L. Goodrum , Jens K. Ramsey , Paul R. Culley , Joseph P. Miller
IPC分类号： G06F13/36 , G06F1/12 , G06F13/40 , G06F13/42 , G06F5/06
CPC分类号： G06F13/405
摘要： Data is transmitted between a first device and a second device connected by the communications channel in a computer system. The first device generates a first clock and the second device generates a second clock. The first clock is provided to the second device and the second clock is provided to the first device. Data received by the first device over the communications channel from the second device is synchronized to the first clock. The receiving logic in the first device includes a first-in-first-out buffer The received data is stored in a first-in-first-out buffer until the data is synchronized to the first clock. The first and second clocks have the same frequency.
摘要翻译：在计算机系统中，通过通信信道连接的第一设备和第二设备之间传送数据。第一设备产生第一时钟，第二设备产生第二时钟。将第一时钟提供给第二设备，并且将第二时钟提供给第一设备。由第一设备通过通信信道从第二设备接收的数据被同步到第一时钟。第一设备中的接收逻辑包括先进先出缓冲器。接收到的数据被存储在先进先出缓冲器中，直到数据与第一时钟同步。第一和第二个时钟具有相同的频率。

8. 发明授权

US5553248A System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal 失效
标题翻译：在检测到锁定的重试信号后中止锁定周期之后，将最高优先级授予微处理器释放系统总线的系统
公开(公告)号：US5553248A
公开(公告)日：1996-09-03
申请号：US956034
申请日：1992-10-02
申请人： Maria L. Melo , Jeff W. Wolford , Michael Moriarty , Paul R. Culley , Arnold T. Schnell
发明人： Maria L. Melo , Jeff W. Wolford , Michael Moriarty , Paul R. Culley , Arnold T. Schnell
IPC分类号： G06F13/36 , G06F13/362 , G06F15/16 , G06F15/177 , G06F13/20 , G06F13/26
CPC分类号： G06F13/36 , G06F13/362
摘要： Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allows a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.
摘要翻译：用于确定几个CPU中的哪一个接收优先级以在多处理器系统中成为主机总线的总线主机的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。在仲裁方案中，主机总线的当前总线主机确定主机总线的控制传输何时由优先级排列方案之一决定。仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。分割事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。即使主机总线被另一个设备控制，数据在空闲时也在主机总线上被断言。

9. 发明授权

US5517624A Multiplexed communication protocol between central and distributed peripherals in multiprocessor computer systems 失效
标题翻译：多处理器计算机系统中的中央和分布式外设之间的多路复用通信协议
公开(公告)号：US5517624A
公开(公告)日：1996-05-14
申请号：US955482
申请日：1992-10-02
申请人： John A. Landry , Dale J. Mayer , Paul R. Culley
发明人： John A. Landry , Dale J. Mayer , Paul R. Culley
IPC分类号： G06F13/32 , G06F13/42 , G06F13/24
CPC分类号： G06F13/4217 , G06F13/32
摘要： A multiplexed communication protocol for broadcasting interrupt, DMA and other miscellaneous data across a bus from a central peripheral device to a plurality of distributed peripheral devices associated with each processor in a multiprocessor computer system. The multiplexed bus includes a data portion and a status portion, where the status portion indicates one of several different cycle types executed on the bus, and where each cycle type further indicates the data asserted on the data portion. The cycle types further include address and data read and write cycles to allow access of the registers in the distributed devices via the multiplexed bus. Thus, system interrupt, address, data, DMA, NMI and miscellaneous cycles are defined where a system interrupt cycle is continually executed on consecutive cycles until interrupted by a request to execute another cycle type. The cycle sequence is implemented to insert system interrupt cycles between the address and data cycles to prevent significant channel latency when system interrupts occur.
摘要翻译：一种多路复用通信协议，用于在多处理器计算机系统中从中央外围设备到与多个处理器计算机系统中的每个处理器相关联的多个分布式外围设备的总线上广播中断，DMA和其他杂项数据。多路复用总线包括数据部分和状态部分，其中状态部分指示在总线上执行的几种不同的周期类型之一，并且其中每个周期类型进一步指示在数据部分上断言的数据。循环类型还包括地址和数据读取和写入周期，以允许通过多路复用总线访问分布式设备中的寄存器。因此，定义系统中断，地址，数据，DMA，NMI和其他周期，其中系统中断周期在连续循环中连续执行，直到被执行另一个循环类型的请求中断。实施循环序列以在地址和数据周期之间插入系统中断周期，以防止系统中断发生时的重要通道延迟。

10. 发明授权

US5437042A Arrangement of DMA, interrupt and timer functions to implement symmetrical processing in a multiprocessor computer system 失效
标题翻译：在多处理器计算机系统中配置DMA，中断和定时器功能以实现对称处理
公开(公告)号：US5437042A
公开(公告)日：1995-07-25
申请号：US955683
申请日：1992-10-02
申请人： Paul R. Culley , John A. Landry , Dale J. Mayer , Christopher C. Wanner , Guy E. McSwain
发明人： Paul R. Culley , John A. Landry , Dale J. Mayer , Christopher C. Wanner , Guy E. McSwain
IPC分类号： G06F13/24 , G06F13/32 , G06F15/80 , G06F13/00
CPC分类号： G06F15/8015 , G06F13/24 , G06F13/32
摘要： An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.
摘要翻译：在多处理器计算机系统中安排直接存储器访问（DMA），中断和定时器功能，以允许对称处理。被认为是所有CPU通用的几个功能以及通过扩展总线方便地访问的那些功能保留在耦合到扩展总线的中央系统外围芯片中。这些中心功能包括DMA控制器的主要部分和控制扩展总线访问的仲裁电路。本地为每个CPU提供了分布式外设，包括可编程中断控制器，多处理器中断逻辑，不可屏蔽中断逻辑，本地DMA逻辑和定时器功能。在中央和分布式外设之间提供总线，以允许中央外设向CPU广播信息，并且当本地CPU在中央外设中编程或访问功能时，将分布式芯片的本地信息提供给中央外设。

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