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1. 发明申请

WO2009042459A1 SINGLE WAFER IMPLANTER FOR SILICON-ON-INSULATOR WAFER FABRICATION 审中-公开
标题翻译：用于绝缘子绝缘子制造的单波长植绒
公开(公告)号：WO2009042459A1
公开(公告)日：2009-04-02
申请号：PCT/US2008/076615
申请日：2008-09-17
申请人： VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. , BLAKE, Julian, G. , EROKHIN, Yuri , ENGLAND, Jonathan, Gerald
发明人： BLAKE, Julian, G. , EROKHIN, Yuri , ENGLAND, Jonathan, Gerald
IPC分类号： H01L21/265
CPC分类号： H01J37/3171 , H01J37/20 , H01J2237/0815 , H01J2237/2001 , H01J2237/31703 , H01L21/67109 , H01L21/6831
摘要： An ion implanter is disclosed. One such ion implanter includes an ion beam source configured to generate oxygen, nitrogen, helium, or hydrogen ions into an ion beam with a specific dose range, and an analyzer magnet configured to remove undesired species from the ion beam. The ion implanter includes an electrostatic chuck having a backside gas thermal coupling that is configured to hold a single workpiece for silicon-on-insulator implantation by the ion beam and is configured to cool the workpiece to a temperature in a range of approximately 300°C to 600°C.
摘要翻译：公开了一种离子注入机。一个这样的离子注入机包括被配置为将氧，氮，氦或氢离子生成到具有特定剂量范围的离子束中的离子束源，以及配置成从离子束去除不需要的物质的分析器磁体。离子注入机包括具有后侧气体热耦合的静电卡盘，其被配置为保持单个工件用于通过离子束进行绝缘体上硅的注入，并且被配置为将工件冷却至约300℃的温度至600℃。

2. 发明申请

WO2006026180A3 REDUCTION OF SOURCE AND DRAIN PARASITIC CAPACITANCE IN CMOS DEVICES 审中-公开
标题翻译：降低CMOS器件中的源极和漏极寄生电容
公开(公告)号：WO2006026180A3
公开(公告)日：2006-08-03
申请号：PCT/US2005029454
申请日：2005-08-18
申请人： VARIAN SEMICONDUCTOR EQUIPMENT , EROKHIN YURI , JEONG UKYO , SCHEUER JAY T , WALTHER STEVEN R
发明人： EROKHIN YURI , JEONG UKYO , SCHEUER JAY T , WALTHER STEVEN R
IPC分类号： H01L21/225 , H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L21/2236 , H01L29/66575
摘要： A method for fabricating a semiconductor-based device includes providing a doped semiconductor substrate, introducing a second dopant into the substrate to define a pn junction, and introducing a neutralizing species into the substrate in the neighborhood of the pn junction to reduce a capacitance associated with the pn junction. A semiconductor-based device includes a semiconductor substrate having first and second dopants, and a neutralizing species. The first and second dopants define a pn junction, and the neutralizing species neutralizes a portion of the first dopant in the neighborhood of the pn junction to decrease a capacitance associated with the pn junction.
摘要翻译：一种用于制造基于半导体的器件的方法包括提供掺杂的半导体衬底，将第二掺杂剂引入到衬底中以限定pn结，并将中和物质引入到pn结附近的衬底中，以减少与 pn结。基于半导体的器件包括具有第一和第二掺杂剂的半导体衬底和中和物质。第一和第二掺杂剂限定pn结，并且中和物质中和pn结附近的第一掺杂剂的一部分以减少与pn结相关联的电容。

3. 发明申请

WO2007092529A8 TECHNIQUES FOR DEPOSITING METALLIC FILMS USING ION IMPLANTATION SURFACE MODIFICATION FOR CATALYSIS OF ELECTROLESS DEPOSITION 审中-公开
标题翻译：使用离子植入表面改性沉积金属膜的技术用于电解沉积的催化
公开(公告)号：WO2007092529A8
公开(公告)日：2008-09-25
申请号：PCT/US2007003315
申请日：2007-02-07
申请人： VARIAN SEMICONDUCTOR EQUIPMENT , NUNAN PETER D , EROKHIN YURI
发明人： NUNAN PETER D , EROKHIN YURI
IPC分类号： C23C18/28 , C23C14/04 , C23C14/48 , C23C18/30 , H01L29/00
CPC分类号： C23C18/1608 , C23C18/1879 , C23C18/32 , C23C18/38 , C23C18/48 , H01L21/28568 , H01L21/32051 , H01L21/76867 , H01L21/76874 , H01L21/76879
摘要： Techniques for deposition metallic films (150) using ion implantation surface modification for catalysis of electroless deposition are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for depositing a metallic film (150). The method may comprise depositing a catalyzing material on a structure (100), wherein the structure (100) comprises a substrate (1 10), a dielectric layer (120) on the substrate ( 1 10), and a resist layer (130) on the dielectric layer (120), wherein the dielectric layer (120) and the resist layer (130 have one or more openings (140). The method may also comprise stripping the resist layer (130). The method may further comprise depositing a metallic film (150) on the catalyzing material in the one or more openings (140) of the structure (100) to fill the one or more openings (140).
摘要翻译：公开了使用离子注入表面修饰用于无电沉积催化的沉积金属膜（150）的技术。在一个特定的示例性实施例中，可以将这些技术实现为用于沉积金属膜（150）的方法。该方法可以包括在结构（100）上沉积催化材料，其中所述结构（100）包括基底（110），所述基底（110）上的介电层（120）和抗蚀剂层（130）在电介质层（120）上，其中电介质层（120）和抗蚀剂层（130）具有一个或多个开口（140），该方法还可以包括剥离抗蚀剂层（130），该方法还可以包括：在所述结构（100）的一个或多个开口（140）中的催化材料上的金属膜（150）以填充所述一个或多个开口（140）。

4. 发明申请

WO2005020307A1 INTERNAL GETTERING IN SIMOX SOI SILICON SUBSTRATES 审中-公开
标题翻译： SIMOX SOI硅基材内部入料
公开(公告)号：WO2005020307A1
公开(公告)日：2005-03-03
申请号：PCT/US2004/025378
申请日：2004-08-05
申请人： IBIS TECHNOLOGY CORPORATION , EROKHIN, Yuri , DEMPSEY, Kevin, J.
发明人： EROKHIN, Yuri , DEMPSEY, Kevin, J.
IPC分类号： H01L21/265
CPC分类号： H01L21/26533 , H01L21/3226
摘要： The present invention provides methods for forming SOI wafers having internal gettering layers for sequestering metallic impurities. More particularly, in one embodiment of the invention, a plurality of sites for sequestering metallic impurities are formed in a silicon substrate by implanting a selected dose of oxygen ions therein. In one embodiment, an epitaxial layer of crystalline silicon is formed over the substrate, and a buried continuous oxide layer is generated in the epitaxial layer, for example, by employing a SIMOX process.
摘要翻译：本发明提供了形成具有用于隔离金属杂质的内部吸气层的SOI晶片的方法。更具体地说，在本发明的一个实施例中，通过在其中注入选定剂量的氧离子，在硅衬底中形成多个用于隔离金属杂质的部位。在一个实施例中，在衬底上形成晶体硅的外延层，并且例如通过使用SIMOX工艺在外延层中产生掩埋的连续氧化物层。

5. 发明申请

WO2009045722A1 TWO-DIEMENSIONAL UNIFORMITY CORRECTION FOR ION BEAM ASSISTED ETCHING 审中-公开
标题翻译：用于离子束辅助蚀刻的双重均匀校正
公开(公告)号：WO2009045722A1
公开(公告)日：2009-04-09
申请号：PCT/US2008/076644
申请日：2008-09-17
申请人： VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. , WALTHER, Steven, R. , NUNAN, Peter, D. , EROKHIN, Yuri
发明人： WALTHER, Steven, R. , NUNAN, Peter, D. , EROKHIN, Yuri
IPC分类号： H01L21/265
CPC分类号： H01J37/3171 , H01J37/244 , H01J37/3045 , H01J37/3053 , H01J2237/24507 , H01J2237/24542 , H01J2237/30477 , H01L21/3065 , H01L22/12
摘要： An approach for providing two-dimensional uniformity correction for ion beam assisted etching is described. In one embodiment, there is a method for ion beam etching a substrate. In this embodiment, an ion implant dose map containing a correlation between implant dose rate and etch rate is retrieved. In addition, a recipe that contains values for ion beam parameters used in the ion beam etching of the substrate is obtained. An ion beam is directed at the surface of the substrate and the surface is etched with the ion beam according to the ion implant dose map and the values of the ion beam parameters in the recipe. The etching of the surface is controlled in accordance with the ion implant dose map and the ion beam parameter values.
摘要翻译：描述了一种用于离子束辅助蚀刻提供二维均匀性校正的方法。在一个实施例中，存在用于离子束蚀刻衬底的方法。在该实施例中，检索包含植入物剂量率和蚀刻速率之间的相关性的离子注入剂量图。此外，获得了包含用于衬底的离子束蚀刻中的离子束参数的值的配方。离子束被引导到衬底的表面，并且根据离子注入剂量图和配方中离子束参数的值，用离子束蚀刻表面。根据离子注入剂量图和离子束参数值来控制表面的蚀刻。

6. 发明申请

WO2003041160A3 TWO-STEP ION IMPLANTATION METHOD WITH ACTIVE WAFER COOLING FOR BURIED OXIDE FORMATION 审中-公开
公开(公告)号：WO2003041160A3
公开(公告)日：2003-05-15
申请号：PCT/US2002/035382
申请日：2002-11-04
申请人： IBIS TECHNOLOGY CORPORATION , EROKHIN, Yuri , BLAKE, Julian, G.
发明人： EROKHIN, Yuri , BLAKE, Julian, G.
IPC分类号： H01L21/76
摘要： The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300 °C to 600 °C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range 50 °C to 150 °C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate. The annealing step can be performed in a third chamber or in either of the first or second chambers.

7. 发明申请

WO2006026180A2 REDUCTION OF SOURCE AND DRAIN PARASITIC CAPACITANCE IN CMOS DEVICES 审中-公开
标题翻译： CMOS器件中源极和漏极寄生电容的降低
公开(公告)号：WO2006026180A2
公开(公告)日：2006-03-09
申请号：PCT/US2005/029454
申请日：2005-08-18
申请人： VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. , EROKHIN, Yuri , JEONG, Ukyo , SCHEUER, Jay, T. , WALTHER, Steven, R.
发明人： EROKHIN, Yuri , JEONG, Ukyo , SCHEUER, Jay, T. , WALTHER, Steven, R.
IPC分类号： H01L21/225 , H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L21/2236 , H01L29/66575
摘要： A method for fabricating a semiconductor-based device includes providing a doped semiconductor substrate, introducing a second dopant into the substrate to define a pn junction, and introducing a neutralizing species into the substrate in the neighborhood of the pn junction to reduce a capacitance associated with the pn junction. A semiconductor-based device includes a semiconductor substrate having first and second dopants, and a neutralizing species. The first and second dopants define a pn junction, and the neutralizing species neutralizes a portion of the first dopant in the neighborhood of the pn junction to decrease a capacitance associated with the pn junction.
摘要翻译：用于制造基于半导体的器件的方法包括提供掺杂的半导体衬底，将第二掺杂剂引入到衬底中以限定pn结，并且将中和物质引入衬底中的邻近衬底 pn结以减小与pn结相关联的电容。基于半导体的器件包括具有第一和第二掺杂剂以及中和物质的半导体衬底。第一和第二掺杂剂限定pn结，并且中和物质中和pn结附近的第一掺杂剂的一部分，以减小与pn结相关的电容。

8. 发明申请

WO2003041160A2 ACTIVE WAFER COOLING DURING DAMAGE ENGINEERING IMPLANT TO ENHANCE BURIED OXIDE FORMATION IN SIMOX WAFERS 审中-公开
标题翻译：在损伤工程中有效的冷却冷却，以增强SIMOX WAFERS中的氧化物形成
公开(公告)号：WO2003041160A2
公开(公告)日：2003-05-15
申请号：PCT/US2002/035382
申请日：2002-11-04
申请人： IBIS TECHNOLOGY CORPORATION , EROKHIN, Yuri , BLAKE, Julian, G.
发明人： EROKHIN, Yuri , BLAKE, Julian, G.
IPC分类号： H01L21/76
CPC分类号： H01L21/76243 , Y10S438/966
摘要： The present invention provides methods and system for forming a buried oxide layer (BOX) region in a semiconductor substrate, such as, a silicon wafer. In one aspect, in a method of the invention, an initial dose of oxygen ions is implanted in the substrate while maintaining the substrate temperature in a range of about 300 °C to 600 °C. Subsequently, a second dose of oxygen ions is implanted in the substrate while actively cooling the substrate to maintain the substrate temperature in range 50 °C to 150 °C. These ion implantation steps are followed by an annealing step in an oxygen containing atmosphere to form a continuous BOX region in the substrate. In one preferred embodiment, the initial ion implantation step is performed in a chamber that includes a device for heating the substrate while the second ion implantation step is performed in a separate chamber that is equipped with a device for actively cooling the substrate. The annealing step can be performed in a third chamber or in either of the first or second chambers.
摘要翻译：本发明提供了在诸如硅晶片的半导体衬底中形成掩埋氧化物层（BOX）区的方法和系统。一方面，在本发明的方法中，将初始剂量的氧离子注入基板中，同时将基板温度保持在约300℃至600℃的范围内。随后，将第二剂量的氧离子注入在衬底中同时主动冷却衬底以将衬底温度保持在50℃至150℃的范围内。这些离子注入步骤之后是在含氧气氛中的退火步骤，以在衬底中形成连续的BOX区域。在一个优选实施例中，初始离子注入步骤在包括用于加热衬底的器件的腔室中执行，而第二离子注入步骤在配备有用于主动冷却衬底的器件的单独室中执行。退火步骤可以在第三室或第一室或第二室中的任一个中进行。

9. 发明申请

WO2012068088A1 DOPING OF PLANAR OR THREE-DIMENSIONAL STRUCTURES AT ELEVATED TEMPERATURES 审中-公开
标题翻译：在高温下排列平面或三维结构
公开(公告)号：WO2012068088A1
公开(公告)日：2012-05-24
申请号：PCT/US2011/060761
申请日：2011-11-15
申请人： VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC. , EROKHIN, Yuri , STEEN, Louis , GOSSMAN, Hans-joachim, L.
发明人： EROKHIN, Yuri , STEEN, Louis , GOSSMAN, Hans-joachim, L.
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L29/66803 , H01L21/2652 , H01L21/26526
摘要： An improved method of doping a workpiece is disclosed. In this method, a film comprising the species to be implanted is introduced to the surface of a planar or three-dimensional workpiece. This film can be grown using CVD, a bath or other means. The workpiece with the film is then subjected to ion bombardment to help drive the dopant into the workpiece. This ion bombardment is performed at elevated temperatures to reduce crystal damage and create a more abrupt doped region.
摘要翻译：公开了一种改进的掺杂工件的方法。在该方法中，将包含被植入物种的膜引入平面或三维工件的表面。这种膜可以使用CVD，浴缸或其他方法种植。然后将具有膜的工件进行离子轰击以帮助将掺杂剂驱动到工件中。这种离子轰击在升高的温度下进行，以减少晶体损伤并产生更陡峭的掺杂区域。

10. 发明申请

WO2009039264A3 WAFER BONDING ACTIVATED BY ION IMPLANTATION 审中-公开
标题翻译：离子植入激活的波形粘结
公开(公告)号：WO2009039264A3
公开(公告)日：2009-05-28
申请号：PCT/US2008076840
申请日：2008-09-18
申请人： VARIAN SEMICONDUCTOR EQUIPMENT , EROKHIN YURI , SULLIVAN PAUL , WALTHER STEVEN R , NUNAN PETER
发明人： EROKHIN YURI , SULLIVAN PAUL , WALTHER STEVEN R , NUNAN PETER
IPC分类号： H01L21/60 , H01L21/265
CPC分类号： H01L21/76251 , H01J37/20 , H01J37/3171 , H01J2237/201 , H01J2237/202 , H01L21/26506 , H01L21/6835 , H01L2221/68359 , H01L2924/30105
摘要： A method for wafer bonding two substrates activated by ion implantation is disclosed. An in situ ion bonding chamber allows ion activation and bonding to occur within an existing process tool utilized in a manufacturing process line. Ion activation of at least one of the substrates is performed at low implant energies to ensure that the wafer material below the thin surface layers remains unaffected by the ion activation.
摘要翻译：公开了一种通过离子注入激活的晶片接合两个基板的方法。原位离子键合室允许在制造生产线中使用的现有工艺工具中发生离子活化和结合。在低注入能量下进行至少一个衬底的离子激活，以确保薄表面层下面的晶片材料不受离子激活的影响。

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