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1. 发明申请

US20140175566A1 CONVERTING A HIGH DIELECTRIC SPACER TO A LOW DIELECTRIC SPACER 审中-公开
标题翻译：将高介电间隔转换为低介电间隔
公开(公告)号：US20140175566A1
公开(公告)日：2014-06-26
申请号：US13722561
申请日：2012-12-20
申请人： Gopinath Bhimarasetti , Walid M. Hafez , Weimin C. Han
发明人： Gopinath Bhimarasetti , Walid M. Hafez , Weimin C. Han
IPC分类号： H01L29/06
CPC分类号： H01L29/66545 , H01L21/3105 , H01L21/823468 , H01L21/823864 , H01L29/4983 , H01L29/66795
摘要： A dielectric constant of spacer material in a transistor is changed from a high-κ dielectric material to a low-κ dielectric material. The process uses oxidation treatments to enable the transformation of the high-κ dielectric material to a low-κ dielectric material.
摘要翻译：晶体管中的间隔物材料的介电常数从高<！ - SIPO

2. 发明申请

US20140001569A1 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS 有权
标题翻译：具有电介质衬底的高电压三维器件
公开(公告)号：US20140001569A1
公开(公告)日：2014-01-02
申请号：US13536732
申请日：2012-06-28
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括由设置在第一鳍片有源区上的第一介电层和设置在第一介电层上的第二不同介电层构成的第一栅极电介质。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括由设置在第二鳍片有源区上的第二介电层构成的第二栅极电介质。

3. 发明申请

US20050238567A1 Tubular carbon nano/micro structures and method of making same 失效
标题翻译：管状碳纳米/微结构及其制作方法
公开(公告)号：US20050238567A1
公开(公告)日：2005-10-27
申请号：US10937738
申请日：2004-09-09
申请人： Mahendra Sunkara , Gopinath Bhimarasetti
发明人： Mahendra Sunkara , Gopinath Bhimarasetti
IPC分类号： D01F9/12 , D01F9/127
CPC分类号： B82Y30/00 , D01F9/127 , Y10T428/2918
摘要： A method of synthesizing and controlling the internal diameters, conical angles, and morphology of tubular carbon nano/micro structures. Different morphologies can be synthesized included but not limited to cones, straight tubes, nozzles, cone-on-tube (funnels), tube-on-cone, cone-tube-cone, n-staged structures, multijunctioned tubes, Y-junctions, dumbbell (pinched morphology) and capsules. The process is based on changing the wetting behavior of a low melting metals such as gallium, indium, and aluminum with carbon using a growth environment of different gas phase chemistries. The described carbon tubular morphologies can be synthesized using any kind of gas phase excitation such as, but not limited to, microwave excitation, hot filament excitation, thermal excitation and Radio Frequency (RF) excitations. The depositions area is only limited by the substrate area in the equipment used and not limited by the process. The internal diameters of the carbon tubular structures can be varied from a few nm to as high as about 20 microns. The wall thickness is about 10-20 nm. The carbon tubular structures can be formed open on both ends are directly applicable to micro-fluidics. Gallium required for the growth of the carbon tubes can be supplied either as a thin film on the substrate or could be supplied through the gas phase with different precursors such as Tri-methyl gallium. Seamless Y-junctions with no internal obstructions can be synthesized without the need of templates. Multi-channeled junctions can also be synthesized without any internal obstructions. Gallium that partially fills the carbon structures can be removed from the tubes by simple heating in vacuum at temperature above 600°.
摘要翻译：一种合成和控制管状碳纳米/微结构的内径，锥角和形态的方法。可以合成不同的形态，但不限于锥体，直管，喷嘴，管中管（漏斗），锥管，锥管锥，n阶段结构，多功能管，Y形结，哑铃（捏形态）和胶囊。该方法基于使用不同气相化学的生长环境来改变低熔点金属如镓，铟和铝与碳的润湿行为。所描述的碳管形态可以使用任何种类的气相激发合成，例如但不限于微波激发，热丝激发，热激发和射频（RF）激发。沉积区仅受所用设备中的基材面积的限制，不受该方法的限制。碳管状结构的内径可以从几nm变化到高达约20微米。壁厚约为10-20nm。碳管结构可以在两端形成开放直接适用于微流体。碳管生长所需的镓可以作为薄膜提供在基底上，或者可以通过气相与诸如三甲基镓的不同前体一起提供。无需模板即可合成无内部障碍物的无缝Y接头。多通道结也可以合成而没有任何内部障碍物。部分填充碳结构的镓可以通过在高于600℃的温度下在真空中简单加热而从管中除去。

4. 发明授权

US10424580B2 Semiconductor devices having modulated nanowire counts 有权
公开(公告)号：US10424580B2
公开(公告)日：2019-09-24
申请号：US13996505
申请日：2011-12-23
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Gopinath Bhimarasetti , Tahir Ghani , Seiyon Kim
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Gopinath Bhimarasetti , Tahir Ghani , Seiyon Kim
IPC分类号： H01L29/775 , H01L21/02 , H01L27/088 , B82Y10/00 , B82Y40/00 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/78 , H01L29/786 , H01L29/16 , B82Y99/00
摘要： Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

5. 发明授权

US09570467B2 High voltage three-dimensional devices having dielectric liners 有权
标题翻译：具有电介质衬垫的高压三维器件
公开(公告)号：US09570467B2
公开(公告)日：2017-02-14
申请号：US14641117
申请日：2015-03-06
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L21/84 , H01L27/12 , H01L29/66 , H01L21/8234 , H01L21/02 , H01L21/28 , H01L29/423 , H01L29/51
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

6. 发明申请

US20130313513A1 SEMICONDUCTOR DEVICES HAVING MODULATED NANOWIRE COUNTS 审中-公开
标题翻译：具有调制纳米级数的半导体器件
公开(公告)号：US20130313513A1
公开(公告)日：2013-11-28
申请号：US13996505
申请日：2011-12-23
申请人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Gopinath Bhimarasetti , Tahir Ghani , Seiyon Kim
发明人： Annalisa Cappellani , Kelin J. Kuhn , Rafael Rios , Gopinath Bhimarasetti , Tahir Ghani , Seiyon Kim
IPC分类号： H01L29/775 , H01L21/02 , H01L27/088
摘要： Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.
摘要翻译：描述了具有调制纳米线计数的半导体器件和形成这种器件的方法。例如，半导体结构包括具有多个纳米线的第一半导体器件，该多个纳米线设置在衬底上并且堆叠在具有第一最上层纳米线的第一垂直平面中。第二半导体器件具有设置在衬底上方的一个或多个纳米线并且堆叠在具有第二最上层纳米线的第二垂直平面中。第二半导体器件包括比第一半导体器件少的一个或多个纳米线。第一和第二最上层的纳米线设置在与第一和第二垂直平面正交的同一平面中。

7. 发明申请

US20160111449A1 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS 有权
公开(公告)号：US20160111449A1
公开(公告)日：2016-04-21
申请号：US14975645
申请日：2015-12-18
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L27/12 , H01L29/66 , H01L29/51 , H01L29/423 , H01L21/8234
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

8. 发明申请

US20150179525A1 HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS 有权
标题翻译：具有电介质衬底的高电压三维器件
公开(公告)号：US20150179525A1
公开(公告)日：2015-06-25
申请号：US14641117
申请日：2015-03-06
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L21/8234 , H01L21/02 , H01L21/28 , H01L29/66
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

9. 发明授权

US08981481B2 High voltage three-dimensional devices having dielectric liners 有权
标题翻译：具有电介质衬垫的高压三维器件
公开(公告)号：US08981481B2
公开(公告)日：2015-03-17
申请号：US13536732
申请日：2012-06-28
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L21/84 , H01L27/12 , H01L21/8234 , H01L29/66
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric composed of a first dielectric layer disposed on the first fin active region, and a second, different, dielectric layer disposed on the first dielectric layer. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric composed of the second dielectric layer disposed on the second fin active region.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括由设置在第一鳍片有源区上的第一介电层和设置在第一介电层上的第二不同介电层构成的第一栅极电介质。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括由设置在第二鳍片有源区上的第二介电层构成的第二栅极电介质。

10. 发明授权

US07597941B2 Tubular carbon nano/micro structures and method of making same 失效
标题翻译：管状碳纳米/微结构及其制作方法
公开(公告)号：US07597941B2
公开(公告)日：2009-10-06
申请号：US10937738
申请日：2004-09-09
申请人： Mahendra Kumar Sunkara , Gopinath Bhimarasetti
发明人： Mahendra Kumar Sunkara , Gopinath Bhimarasetti
IPC分类号： H05H1/24 , D01F9/12 , B32B9/00
CPC分类号： B82Y30/00 , D01F9/127 , Y10T428/2918
摘要： A method of synthesizing and controlling the internal diameters, conical angles, and morphology of tubular carbon nano/micro structures. Different morphologies can be synthesized included but not limited to cones, straight tubes, nozzles, cone-on-tube (funnels), tube-on-cone, cone-tube-cone, n-staged structures, multijunctioned tubes, Y-junctions, dumbbell (pinched morphology) and capsules. The process is based on changing the wetting behavior of a low melting metals such as gallium, indium, and aluminum with carbon using a growth environment of different gas phase chemistries. The described carbon tubular morphologies can be synthesized using any kind of gas phase excitation such as, but not limited to, microwave excitation, hot filament excitation, thermal excitation and Radio Frequency (RF) excitations. The depositions area is only limited by the substrate area in the equipment used and not limited by the process. The internal diameters of the carbon tubular structures can be varied from a few nm to as high as about 20 microns. The wall thickness is about 10-20 nm. The carbon tubular structures can be formed open on both ends are directly applicable to micro-fluidics. Gallium required for the growth of the carbon tubes can be supplied either as a thin film on the substrate or could be supplied through the gas phase with different precursors such as Tri-methyl gallium. Seamless Y-junctions with no internal obstructions can be synthesized without the need of templates. Multi-channeled junctions can also be synthesized without any internal obstructions. Gallium that partially fills the carbon structures can be removed from the tubes by simple heating in vacuum at temperature above 600°.
摘要翻译：一种合成和控制管状碳纳米/微结构的内径，锥角和形态的方法。可以合成不同的形态，但不限于锥体，直管，喷嘴，管中管（漏斗），锥管，锥管锥，n阶段结构，多功能管，Y形结，哑铃（捏形态）和胶囊。该方法基于使用不同气相化学的生长环境来改变低熔点金属如镓，铟和铝与碳的润湿行为。所描述的碳管形态可以使用任何种类的气相激发合成，例如但不限于微波激发，热丝激发，热激发和射频（RF）激发。沉积区仅受所用设备中的基材面积的限制，不受该方法的限制。碳管状结构的内径可以从几nm变化到高达约20微米。壁厚约为10-20nm。碳管结构可以在两端形成开放直接适用于微流体。碳管生长所需的镓可以作为薄膜提供在基底上，或者可以通过气相与诸如三甲基镓的不同前体一起提供。无需模板即可合成无内部障碍物的无缝Y接头。多通道结也可以合成而没有任何内部障碍物。部分填充碳结构的镓可以通过在高于600℃的温度下在真空中简单加热而从管中除去。

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