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1. 发明授权

US07546227B2 Segmentation and interpolation of current waveforms 有权
标题翻译：电流波形的分段和插值
公开(公告)号：US07546227B2
公开(公告)日：2009-06-09
申请号：US12184218
申请日：2008-07-31
申请人： Harold J. Levy
发明人： Harold J. Levy
IPC分类号： G06F17/10 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (within a desired tolerance). The beginning and ending current/time values for each segment can then be compiled into the piecewise linear representation of the driver output current signal. A method for generating a model driver output current signal includes conformally mapping first and second sets of precharacterization output current data based on a weighted average of the indexing parameter (e.g., input slew or output capacitance) values for the model driver output signal and the first and second sets of precharacterization data.
摘要翻译：用于产生驱动器输出电流信号的线性分段表示的方法包括分割驱动器输出电流信号，使得每个段的积分与相关联的输出电压信号的相应部分中的实际电压变化匹配（在期望的公差内）。然后可以将每个段的开始和结束当前/时间值编译成驱动器输出电流信号的分段线性表示。一种用于产生模型驱动器输出电流信号的方法包括：基于模型驱动器输出信号的索引参数（例如，输入转换或输出电容）值的加权平均值，第一和第二组先验特性输出电流数据的第一和第二组和第二组预特征数据。

2. 发明申请

US20080288223A1 Segmentation And Interpolation Of Current Waveforms 有权
标题翻译：电流波形的分割和插值
公开(公告)号：US20080288223A1
公开(公告)日：2008-11-20
申请号：US12184218
申请日：2008-07-31
申请人： Harold J. Levy
发明人： Harold J. Levy
IPC分类号： G06F17/10
CPC分类号： G06F17/5036
摘要： A method for generating a linear piecewise representation of a driver output current signal includes segmenting the driver output current signal such that an integral of each segment matches an actual voltage change in corresponding portion of an associated output voltage signal (within a desired tolerance). The beginning and ending current/time values for each segment can then be compiled into the piecewise linear representation of the driver output current signal. A method for generating a model driver output current signal includes conformally mapping first and second sets of precharacterization output current data based on a weighted average of the indexing parameter (e.g., input slew or output capacitance) values for the model driver output signal and the first and second sets of precharacterization data.
摘要翻译：用于产生驱动器输出电流信号的线性分段表示的方法包括分割驱动器输出电流信号，使得每个段的积分与相关联的输出电压信号的相应部分中的实际电压变化匹配（在期望的公差内）。然后可以将每个段的开始和结束当前/时间值编译成驱动器输出电流信号的分段线性表示。一种用于产生模型驱动器输出电流信号的方法包括：基于模型驱动器输出信号的索引参数（例如，输入转换或输出电容）值的加权平均值，第一和第二组先验特性输出电流数据的第一和第二组和第二组预特征数据。

3. 发明授权

US5745407A Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same 失效
标题翻译：无晶体管，多电流电流模式存储单元和存储器阵列以及读写方法
公开(公告)号：US5745407A
公开(公告)日：1998-04-28
申请号：US628821
申请日：1996-04-05
申请人： Harold J. Levy , Thomas C. McGill
发明人： Harold J. Levy , Thomas C. McGill
IPC分类号： G11C11/39 , G11C11/56 , H01L27/102 , G11C11/00 , G11C11/36 , H01L27/108
CPC分类号： H01L27/1021 , G11C11/39 , G11C11/56 , G11C2211/5614 , Y10S438/979
摘要： A transistorless memory cell for storing information as one of two possible bistable current states comprises (i) at least one first transistorless device exhibiting N-type negative differential resistance, including a high-impedance region, a low-impedance region and a negative-resistance region and having a polarity and (ii) at least one second transistorless device exhibiting an exponential or linear current-voltage characteristic and coupled to the first transistorless device. The read/write operation of the transistorless memory cell is performed in a current mode. A method for fabricating a self-aligned, three-dimensional structure of memory cells comprises the steps of (i) forming a first conducting layer, (ii) forming a first semiconductor layer above the first conducting layer, (iii) forming a second semiconductor layer above the first semiconductor layer, (iv) patterning the second semiconductor layer, (v) etching the second semiconductor layer, the first semiconductor layer and the first conducting layer, (vi) forming a second conducting layer above the second semiconductor layer, (vii) patterning and etching the second conducting layer, and (viii) etching the second semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a second kind, and etching the first semiconductor layer using the second conducting layer as a mask to form multiple semiconducting devices of a first kind, wherein the semiconducting devices of the first kind exhibit N-type negative differential resistance, and the semiconducting devices of the second kind may exhibit exponential or linear current-voltage characteristics.
摘要翻译：用于将信息存储为两个可能的双稳电流状态之一的无晶体管存储单元包括：（i）至少一个具有N型负差分电阻的第一无晶体管器件，包括高阻抗区域，低阻抗区域和负电阻区域并具有极性，以及（ii）呈现指数或线性电流 - 电压特性并耦合到第一无晶体管器件的至少一个第二无晶体管器件。无电晶体管存储单元的读/写操作在当前模式下执行。一种用于制造存储单元的自对准三维结构的方法包括以下步骤：（i）形成第一导电层，（ii）在第一导电层上形成第一半导体层，（iii）形成第二半导体（iv）图案化第二半导体层，（v）蚀刻第二半导体层，第一半导体层和第一导电层，（vi）在第二半导体层上形成第二导电层（ vii）图案化和蚀刻第二导电层，以及（viii）使用第二导电层作为掩模蚀刻第二半导体层以形成第二种导电层的多个半导体器件，并且使用第二导电层作为第一导电层来蚀刻第一半导体层掩模形成第一种半导体器件，其中第一类半导体器件表现出N型负微分电阻，半导体器件第二种的导电装置可以呈现指数或线性的电流 - 电压特性。

4. 发明授权

US07725854B2 Nonlinear receiver model for gate-level delay calculation 有权
标题翻译：门级延迟计算的非线性接收机模型
公开(公告)号：US07725854B2
公开(公告)日：2010-05-25
申请号：US11866981
申请日：2007-10-03
申请人： Harold J. Levy
发明人： Harold J. Levy
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036
摘要： A characterized cell library for EDA tools includes receiver model data that provides two or more capacitance values for a given receiver modeling situation (signal type and operating conditions). The receiver model can then use different capacitance values to generate different portions of the model receiver signal, thereby enabling more accurate matching of actual receiver signal timing characteristics. For example, a two-capacitance receiver model can be generated by using the first capacitance value to match the delay characteristics of an actual receiver, and by using the second capacitance (in light of the use of the first capacitance) to match the slew characteristics of that actual receiver. Because typical EDA timing analyses focus mainly on delay and slew (and not the detailed profile of circuit signals), a two-capacitance receiver model can provide a high degree of accuracy without significantly increasing cell library size and computational complexity.
摘要翻译：用于EDA工具的特征化单元库包括接收器模型数据，其为给定的接收机建模情况（信号类型和操作条件）提供两个或多个电容值。接收机模型然后可以使用不同的电容值来产生模型接收机信号的不同部分，从而使得实际的接收机信号时序特征能够更准确地匹配。例如，可以通过使用第一电容值来匹配实际接收机的延迟特性，并且通过使用第二电容（根据使用第一电容）来产生双电容接收器模型以匹配转换特性的实际接收器。因为典型的EDA定时分析主要集中在延迟和转换（而不是电路信号的详细曲线）上，因此双电容接收机模型可以提供高精确度，而不会显着增加单元库大小和计算复杂度。

5. 发明授权

US07496863B2 Nonlinear driver model for multi-driver systems 失效
标题翻译：用于多驱动器系统的非线性驱动器模型
公开(公告)号：US07496863B2
公开(公告)日：2009-02-24
申请号：US11779156
申请日：2007-07-17
申请人： Harold J. Levy
发明人： Harold J. Levy
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5036
摘要： A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.
摘要翻译：用于EDA工具的预特征细胞库包括驱动器模型数据，其包括由输出电压索引的输出电流信号。然后，驱动器模型可以通过使用输出电压内插输出电流信号来产生模型输出，以产生输出电流。然后可以使用输出电流来在预定的时间增量上产生更新的输出电压。然后可以使用更新的输出电压对输出电流信号进行内插，以产生新的输出电流，该输出电流可用于在下一次增量时再次更新输出电压。通过在模型输出信号的时间框架内重复该过程，可以生成与多驱动器系统中的驱动器的实际输出电流和电压信号相匹配的模型输出电流和输出电压信号。

6. 发明授权

US06810506B1 Methodology for stitching reduced-order models of interconnects together 失效
标题翻译：将互连的低阶模型拼接在一起的方法
公开(公告)号：US06810506B1
公开(公告)日：2004-10-26
申请号：US10152408
申请日：2002-05-20
申请人： Harold J. Levy
发明人： Harold J. Levy
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/5022
摘要： A computer implemented method of producing a reduced order model of an electronic circuit to model the connection of two or more circuits. Arnoldi reduced order models for nodes of circuits to be interconnected may be computed. A set of modified nodal analysis matrices for the combination of the two circuits may be constructed. A rank one update may be applied to the modified set of nodal analysis matrices to produce a reduced order model of the combined electronic circuits. In this novel manner, a reduced order model for a combination of circuits may be produced from the individual reduced order models of the individual circuits without the need to recompute the reduced order models of the original circuits, and without the need of the original parasitic network models. The resulting reduced order model may be used in a variety ways consistent with well known uses of such matrices within the field of electronic design automation.
摘要翻译：一种用于产生电子电路的简化模型以对两个或更多个电路的连接进行建模的计算机实现的方法。可以计算Arnoldi减少的要互连的电路节点的次序模型。可以构造用于两个电路的组合的一组修改的节点分析矩阵。可以对经修改的节点分析矩阵集合应用一级更新以产生组合的电子电路的降序模型。以这种新颖的方式，可以从各个电路的各个降阶模型产生用于电路组合的简化阶模型，而不需要重新计算原始电路的降序模型，并且不需要原始寄生网络楷模。所得到的降序模型可以以与电子设计自动化领域内的这种矩阵的众所周知的使用一致的多种方式来使用。

7. 发明授权

US08266559B2 Nonlinear driver model for multi-driver systems 有权
标题翻译：用于多驱动器系统的非线性驱动器模型
公开(公告)号：US08266559B2
公开(公告)日：2012-09-11
申请号：US13052972
申请日：2011-03-21
申请人： Harold J. Levy
发明人： Harold J. Levy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.
摘要翻译：用于EDA工具的预特征细胞库包括驱动器模型数据，包括由输出电压索引的输出电流信号。然后，驱动器模型可以通过使用输出电压内插输出电流信号来产生模型输出，以产生输出电流。然后可以使用输出电流来在预定的时间增量上产生更新的输出电压。然后可以使用更新的输出电压对输出电流信号进行内插，以产生新的输出电流，然后可以在下一次增量时再次更新输出电压。通过在模型输出信号的时间框架内重复该过程，可以生成与多驱动器系统中的驱动器的实际输出电流和电压信号相匹配的模型输出电流和输出电压信号。

8. 发明授权

US08069424B2 Generating a base curve database to reduce storage cost 失效
标题翻译：生成基线曲线数据库以降低存储成本
公开(公告)号：US08069424B2
公开(公告)日：2011-11-29
申请号：US12212606
申请日：2008-09-17
申请人： Xin Wang , Harold J. Levy , Michael N. Misheloff
发明人： Xin Wang , Harold J. Levy , Michael N. Misheloff
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.
摘要翻译：由EDA工具可访问的增强库可以包括基线曲线数据库和多个曲线数据集。每个曲线数据集是指具有某些定时特性的标准单元。为了确定这些时序特性，每个曲线数据集识别至少一个基本曲线（在基线曲线数据库中）以及启动电流，峰值电流，峰值电压和峰值时间。在一个实施例中，每个基本曲线可以被归一化。基本曲线，起始电流，峰值电流，峰值电压和峰值时间可以精确地模拟IC器件的功能，例如，由I（V）曲线表示。

9. 发明申请

US20110173580A1 Nonlinear Driver Model For Multi-Driver Systems 有权
标题翻译：用于多驱动器系统的非线性驱动器模型
公开(公告)号：US20110173580A1
公开(公告)日：2011-07-14
申请号：US13052972
申请日：2011-03-21
申请人： Harold J. Levy
发明人： Harold J. Levy
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.
摘要翻译：用于EDA工具的预特征细胞库包括驱动器模型数据，包括由输出电压索引的输出电流信号。然后，驱动器模型可以通过使用输出电压内插输出电流信号来产生模型输出，以产生输出电流。然后可以使用输出电流来在预定的时间增量上产生更新的输出电压。然后可以使用更新的输出电压对输出电流信号进行内插，以产生新的输出电流，然后可以在下一次增量时再次更新输出电压。通过在模型输出信号的时间框架内重复该过程，可以生成与多驱动器系统中的驱动器的实际输出电流和电压信号相匹配的模型输出电流和输出电压信号。

10. 发明授权

US07913200B2 Nonlinear driver model for multi-driver systems 有权
标题翻译：用于多驱动器系统的非线性驱动器模型
公开(公告)号：US07913200B2
公开(公告)日：2011-03-22
申请号：US12353136
申请日：2009-01-13
申请人： Harold J. Levy
发明人： Harold J. Levy
IPC分类号： G06F17/50 , G06F19/00 , G06F11/22
CPC分类号： G06F17/5036
摘要： A precharacterized cell library for EDA tools includes driver model data includes output current signals indexed by output voltages. The driver model can then generate a model output by interpolating the output current signals using the output voltage to generate an output current. The output current can then be used to generate an updated output voltage across a predetermined time increment. The output current signals can then be interpolated using the updated output voltage to generate a new output current, when can be used to update the output voltage once again across the next time increment. By repeating this process across a time frame for the model output signal, a model output current and output voltage signals can be generated that match the actual output current and voltage signals from a driver in a multi-driver system.
摘要翻译：用于EDA工具的预特征细胞库包括驱动器模型数据，其包括由输出电压索引的输出电流信号。然后，驱动器模型可以通过使用输出电压内插输出电流信号来产生模型输出，以产生输出电流。然后可以使用输出电流来在预定的时间增量上产生更新的输出电压。然后可以使用更新的输出电压对输出电流信号进行内插，以产生新的输出电流，何时可以在下一次增量时再次更新输出电压。通过在模型输出信号的时间框架内重复该过程，可以生成与多驱动器系统中的驱动器的实际输出电流和电压信号相匹配的模型输出电流和输出电压信号。

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