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1. 发明授权

US07444605B2 Generating a base curve database to reduce storage cost 失效
标题翻译：生成基线曲线数据库以降低存储成本
公开(公告)号：US07444605B2
公开(公告)日：2008-10-28
申请号：US11245550
申请日：2005-10-06
申请人： Xin Wang , Harold J. Levy , Michael N. Misheloff
发明人： Xin Wang , Harold J. Levy , Michael N. Misheloff
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.
摘要翻译：由EDA工具可访问的增强库可以包括基线曲线数据库和多个曲线数据集。每个曲线数据集是指具有某些定时特性的标准单元。为了确定这些时序特性，每个曲线数据集识别至少一个基本曲线（在基线曲线数据库中）以及启动电流，峰值电流，峰值电压和峰值时间。在一个实施例中，每个基本曲线可以被归一化。基本曲线，起始电流，峰值电流，峰值电压和峰值时间可以精确地模拟IC器件的功能，例如，由I（V）曲线表示。

2. 发明授权

US08069424B2 Generating a base curve database to reduce storage cost 失效
标题翻译：生成基线曲线数据库以降低存储成本
公开(公告)号：US08069424B2
公开(公告)日：2011-11-29
申请号：US12212606
申请日：2008-09-17
申请人： Xin Wang , Harold J. Levy , Michael N. Misheloff
发明人： Xin Wang , Harold J. Levy , Michael N. Misheloff
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.
摘要翻译：由EDA工具可访问的增强库可以包括基线曲线数据库和多个曲线数据集。每个曲线数据集是指具有某些定时特性的标准单元。为了确定这些时序特性，每个曲线数据集识别至少一个基本曲线（在基线曲线数据库中）以及启动电流，峰值电流，峰值电压和峰值时间。在一个实施例中，每个基本曲线可以被归一化。基本曲线，起始电流，峰值电流，峰值电压和峰值时间可以精确地模拟IC器件的功能，例如，由I（V）曲线表示。

3. 发明申请

US20090013291A1 Generating A Base Curve Database To Reduce Storage Cost 失效
标题翻译：生成基础曲线数据库以降低存储成本
公开(公告)号：US20090013291A1
公开(公告)日：2009-01-08
申请号：US12212606
申请日：2008-09-17
申请人： Xin Wang , Harold J. Levy , Michael N. Misheloff
发明人： Xin Wang , Harold J. Levy , Michael N. Misheloff
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： An enhanced library accessible by an EDA tool can include a base curve database and a plurality of curve data sets. Each curve data set refers to a standard cell having certain timing characteristics. To determine those timing characteristics, each curve data set identifies at least one base curve (in the base curve database) as well as a starting current, a peak current, a peak voltage, and a peak time. In one embodiment, each base curve can be normalized. The base curve(s), the starting current, peak current, peak voltage, and peak time can accurately model the functioning of the IC device, e.g. represented by an I(V) curve.
摘要翻译：由EDA工具可访问的增强库可以包括基线曲线数据库和多个曲线数据集。每个曲线数据集是指具有某些定时特性的标准单元。为了确定这些时序特性，每个曲线数据集识别至少一个基本曲线（在基线曲线数据库中）以及启动电流，峰值电流，峰值电压和峰值时间。在一个实施例中，每个基本曲线可以被归一化。基本曲线，起始电流，峰值电流，峰值电压和峰值时间可以精确地模拟IC器件的功能，例如，由I（V）曲线表示。

4. 发明授权

US5815416A Method of measuring energy consumption in a circuit simulator 失效
标题翻译：测量电路模拟器能耗的方法
公开(公告)号：US5815416A
公开(公告)日：1998-09-29
申请号：US634798
申请日：1996-04-19
申请人： Peter Liebmann , Michael N. Misheloff , David C. Chapman
发明人： Peter Liebmann , Michael N. Misheloff , David C. Chapman
IPC分类号： G01R21/133 , G06F17/50 , G01R21/06
CPC分类号： G01R21/133 , G06F17/5036 , G06F2217/78
摘要： In a computer implemented circuit simulator, a method is provided for measuring energy consumption of a circuit under test during a measurement interval. The method comprises a series of computer implemented steps. A supply voltage is applied to the circuit under test. A current flowing through the circuit under test is then measured. A mirror voltage, representative of the value of the current, is generated. A capacitor is charged, with a power parameter voltage equal to the product of the supply voltage and the mirror voltage, during the measurement interval. An accumulated voltage is measured across the capacitor, wherein the accumulated voltage is representative of energy consumed by the circuit under test.
摘要翻译：在计算机实现的电路模拟器中，提供了一种用于在测量间隔期间测量被测电路的能量消耗的方法。该方法包括一系列计算机实现的步骤。电源电压被施加到被测电路。然后测量流过被测电路的电流。产生代表电流值的反射镜电压。在测量间隔期间，电容器充电，功率参数电压等于电源电压和镜像电压的乘积。在电容器两端测量累积电压，其中累积电压代表被测电路消耗的能量。

5. 发明授权

US5548526A Timing model and characterization system for logic simulation of integrated circuits 失效
标题翻译：集成电路逻辑仿真的时序模型和表征系统
公开(公告)号：US5548526A
公开(公告)日：1996-08-20
申请号：US849242
申请日：1992-03-11
申请人： Michael N. Misheloff
发明人： Michael N. Misheloff
IPC分类号： G06F17/50 , G06F17/10 , G06F17/17
CPC分类号： G06F17/5022
摘要： A method approximates propagation delay through a logic device. Operation of the logic device is divided into a first region and a second region. A boundary between the first region and the second is based on duration of input ramp to the logic device and amount of capacitive load driven by the logic device. For example, the boundary between the first region and the second occurs where for each value of the capacitive load, an output ramp for the logic device is one half complete when the input ramp is complete. When the logic device operates in the first region, a first formula is used to obtain a first value representing delay through the logic device. The first formula varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device. When the logic device operates in the second region, a second formula is used to obtain the first value. The second formula also varies the first value based on the duration of the input ramp to the logic device and the capacitive load driven by the logic device.
摘要翻译：一种方法通过逻辑器件近似传播延迟。逻辑器件的操作被分为第一区域和第二区域。第一区域和第二区域之间的边界基于逻辑器件的输入斜坡的持续时间和逻辑器件驱动的容性负载量。例如，发生第一区域和第二区域之间的边界，对于容性负载的每个值，当输入斜坡完成时，逻辑器件的输出斜坡为一半。当逻辑设备在第一区域中操作时，使用第一公式来获得表示通过逻辑设备的延迟的第一值。第一个公式根据逻辑器件输入斜坡的持续时间和由逻辑器件驱动的容性负载来改变第一个值。当逻辑设备在第二区域中操作时，使用第二公式来获得第一值。第二个公式还根据逻辑器件输入斜坡的持续时间和由逻辑器件驱动的容性负载来改变第一个值。

6. 发明授权

US06751579B1 Method of scaling table based cell library timing models in order to take into account process, temperature and power supply 失效
标题翻译：为了考虑过程，温度和电源，缩放基于表的单元库时序模型的方法
公开(公告)号：US06751579B1
公开(公告)日：2004-06-15
申请号：US09264770
申请日：1999-03-09
申请人： Michael N. Misheloff , Paul R. Findley
发明人： Michael N. Misheloff , Paul R. Findley
IPC分类号： G06F1710
CPC分类号： G06F17/5022
摘要： A method is presented for generating a timing model for a logic cell. Output load indices (Load1, Load2, . . . ,Loadm) are selected which specify output load for the first logic cell. Input ramp indices (IR1, IR2, . . . ,IRn) are selected which specify input ramp for the first logic cell. Baseline output ramp values (ORbl [j,k]) are generated for each output load index (Loadj) and input ramp index (IRk) pair. In order to take into account process, power and temperature variations, scaling factors are used to scale the indices. For example these scaling factors can be utilized for many different logic cells in a cell library. In one embodiment, the output load indices are scaled by a first scaling factor (&lgr;). The input ramp indices are scaled by a second scaling factor (&rgr;). Scaled output ramp values (ORscaled [j,k]) are generated for each scaled output load index and scaled input ramp index pair. A third scaling factor (&ggr;) is used to generate the scaled output ramp values (ORscaled [j,k]). Additionally, delay values can be generated as well. Specifically, baseline delay values (Delaybl [j, k]) are generated for each output load index (Loadj) and input ramp index (IRk) pair. Scaled delay values (Delayscaled [j, k]) are generated for each scaled output load index and scaled input ramp index pair.
摘要翻译：提出了一种用于生成逻辑单元的定时模型的方法。选择输出负载指数（Load1，Load2，...，Loadm），指定第一个逻辑单元的输出负载。选择输入斜坡指数（IR1，IR2，...，IRn），其指定第一逻辑单元的输入斜坡。对于每个输出负载指数（Loadj）和输入斜坡指数（IRk）对，产生基线输出斜坡值（ORbl [j，k]）。为了考虑过程，功率和温度变化，使用比例因子来缩放指数。例如，这些缩放因子可以用于细胞库中的许多不同的逻辑单元。在一个实施例中，通过第一缩放因子（lambda）来缩放输出负载指数。输入斜坡指数按第二比例因子（rho）缩放。对于每个缩放的输出负载指数和缩放输入斜坡索引对，都会生成缩放输出斜坡值（ORscaled [j，k]）。第三比例因子（gamma）用于产生缩放的输出斜坡值（ORscaled [j，k]）。另外，也可以生成延迟值。具体来说，为每个输出负载指数（Loadj）和输入斜坡指数（IRk）对生成基线延迟值（Delaybl [j，k]）。对于每个缩放的输出负载指数和缩放输入斜坡指数对，都会生成缩放延迟值（Delayscaled [j，k]）。

7. 发明授权

US5903468A Determining maximum load index for tabular timing models 失效
标题翻译：确定表格时间模型的最大负载指数
公开(公告)号：US5903468A
公开(公告)日：1999-05-11
申请号：US767780
申请日：1996-12-17
申请人： Michael N. Misheloff , Sabita Jasty
发明人： Michael N. Misheloff , Sabita Jasty
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5022
摘要： In accordance with the preferred embodiment of the present invention, a logic cell library is built. Within the logic cell library a timing model for a first logic cell is generated. In order to generate the timing model a number of indices which specify input ramp for the first logic cell is selected. Also, a number of indices which specify output load for the first logic cell is selected. Also selected are a minimum value for the input ramp and a maximum value for the input ramp. A maximum output load for the timing model is calculated. This is done by calculating, for every input transition in the logic cell which causes an output transition, an intermediate value to be an output load value which results in the first logic cell producing an output signal to the first logic cell which has the maximum value for the input ramp when an input signal to the logic cell has the minimum value for the input ramp. The maximum output load is chosen to be a minimum of the calculated intermediate values.
摘要翻译：根据本发明的优选实施例，构建了逻辑单元库。在逻辑单元库内，生成第一逻辑单元的定时模型。为了产生定时模型，选择指定第一逻辑单元的输入斜坡的多个索引。此外，选择指定第一逻辑单元的输出负载的多个索引。还选择输入斜坡的最小值和输入斜坡的最大值。计算定时模型的最大输出负载。这是通过计算对于导致输出转换的逻辑单元中的每个输入转换，中间值作为输出负载值，其导致第一逻辑单元产生具有最大值的第一逻辑单元的输出信号对于输入斜坡，当逻辑单元的输入信号具有输入斜坡的最小值时。最大输出负载被选择为计算的中间值的最小值。

8. 发明授权

US5625803A Slew rate based power usage simulation and method 失效
标题翻译：基于压摆率的电力使用模拟和方法
公开(公告)号：US5625803A
公开(公告)日：1997-04-29
申请号：US357843
申请日：1994-12-14
申请人： Andrew J. McNelly , Michael R. Grossman , Harish K. Sarin , Bruce S. Seiler , Michael N. Misheloff
发明人： Andrew J. McNelly , Michael R. Grossman , Harish K. Sarin , Bruce S. Seiler , Michael N. Misheloff
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A power usage simulator generates, for all the logic cells in a circuit cell library, a power model that characterizes a cell's power consumption behavior as a two-part, piecewise-linear function based on signal slew rates and output load. A logic simulator is modified so that for each signal transition in a specified logic circuit, the logic simulator performs a power usage computation utilizing the power usage model for all cells affected by each signal transition. The power usage value for each signal transition is posted to a power usage output data structure, with each posted power usage value having an associated time value. The posted power usage values are then analyzed by (A) accumulating the posted power usage values to provide a total power usage value, and (B) clocking the accumulation of power usage values with an end user set clock rate so as to produce a power usage profile indicating the time varying rate of power consumption during the simulation time period. The clocked accumulation of power usage enables easy detection of whether the peak rate of power consumption during the simulation time exceeds a specified threshold (e.g., a threshold associated with a particular power bus design). Thus, data generated by the power usage simulation may be used, either directly or indirectly to determine that the simulated logic circuit requires a larger power bus design, or that the logic circuit should be modified so as to reduce its peak power usage rate.
摘要翻译：功率使用模拟器针对电路单元库中的所有逻辑单元产生将单元的功耗特性表征为基于信号转换速率和输出负载的两部分分段线性函数的功率模型。修改逻辑模拟器，使得对于指定逻辑电路中的每个信号转换，逻辑模拟器利用受每个信号转换影响的所有单元的功率使用模型来执行功率使用计算。每个信号转换的功率使用值被张贴到功率使用输出数据结构，其中每个发布的功率使用值具有相关联的时间值。然后通过（A）累积发布的功率使用值以提供总功率使用值来分析所发布的功率使用值，以及（B）以最终用户设置的时钟速率计时功率使用值的累积，以产生功率指示模拟时间段内的功耗时间变化率的使用情况。功率使用的时钟累积使得能够容易地检测在模拟时间期间的功率消耗的峰值速率是否超过指定阈值（例如，与特定功率总线设计相关联的阈值）。因此，可以直接或间接地使用由功率使用模拟产生的数据，以确定仿真逻辑电路需要更大的功率总线设计，或者应该修改逻辑电路以降低其峰值功率使用率。

9. 发明授权

US5559715A Timing model and characterization system for logic simulation of integrated circuits which takes into account process, temperature and power supply variations 失效
标题翻译：考虑到过程，温度和电源变化的集成电路逻辑仿真的定时模型和表征系统
公开(公告)号：US5559715A
公开(公告)日：1996-09-24
申请号：US219585
申请日：1994-03-28
申请人： Michael N. Misheloff
发明人： Michael N. Misheloff
IPC分类号： G01R31/28 , G06F17/50 , H01L21/82 , G06F17/10
CPC分类号： G06F17/5022
摘要： A method determines approximate propagation delay through logic devices within a library. Each logic cell within the library is characterized at baseline conditions to obtain parameters for each logic cell which define propagation delay through each logic cell at the baseline conditions. A subset of the logic cells are characterized at conditions varying from the baseline conditions to obtain scaling parameters. The scaling parameters modify values of the parameters for all logic cells within the library in order to approximate changes in propagation delay through each logic cell resulting from changes in the baseline conditions. In the preferred embodiment, the conditions varying from the baseline conditions includes a change in at least one of operating temperature, power supply voltage and process conditions.
摘要翻译：一种方法通过库中的逻辑器件来确定近似传播延迟。库内的每个逻辑单元在基线条件下被表征，以获得每个逻辑单元的参数，其定义在基线条件下通过每个逻辑单元的传播延迟。逻辑单元的子集在从基线条件变化的条件下表征，以获得缩放参数。缩放参数修改库内所有逻辑单元的参数值，以便近似基于条件变化导致的每个逻辑单元的传播延迟的变化。在优选实施例中，从基线条件变化的条件包括工作温度，电源电压和工艺条件中的至少一个的变化。

10. 发明授权

US5461579A Extraction method for automated determination of source/drain resistance 失效
标题翻译：用于自动确定源/漏电阻的提取方法
公开(公告)号：US5461579A
公开(公告)日：1995-10-24
申请号：US241268
申请日：1994-05-11
申请人： Michael N. Misheloff , Balaji Krishnamachary , Osman E. Akcasu
发明人： Michael N. Misheloff , Balaji Krishnamachary , Osman E. Akcasu
IPC分类号： H01L21/66 , H01L21/82
CPC分类号： H01L22/20
摘要： A method estimates source resistance for a transistor. A substrate region under a gate for the transistor is modeled as a gate region having a uniform resistivity .rho..sub.g. A source of the transistor is modeled as a source region having a uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s1 are used to calculate a first current from the source of the transistor to a drain of the transistor. The source of the transistor is then modeled as a source region having another uniform resistivity .rho..sub.s2. The uniform resistivity .rho..sub.s2, is different in value than uniform resistivity .rho..sub.s1. The uniform resistivity .rho..sub.g and the uniform resistivity .rho..sub.s2 are used to calculate a second current from the source of the transistor to a drain of the transistor. The uniform resistivity .rho..sub.s1, the uniform resistivity .rho..sub.s2, the first current and the second current are used to calculate the source resistance for the transistor.
摘要翻译：一种估计晶体管的源极电阻的方法。用于晶体管的栅极下面的衬底区域被建模为具有均匀电阻率rho g的栅极区域。晶体管的源被建模为具有均匀电阻率rho s1的源极区域。均匀电阻率rho g和均匀电阻率rho s1用于计算从晶体管的源极到晶体管的漏极的第一电流。然后将晶体管的源模型化为具有另一均匀电阻率rho s2的源极区域。均匀电阻率rho s2的值与均匀电阻率rho s1不同。使用均匀电阻率rho g和均匀电阻率rho s2来计算从晶体管的源极到晶体管的漏极的第二电流。使用均匀电阻率rho s1，均匀电阻率rho s2，第一电流和第二电流来计算晶体管的源极电阻。

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