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    • 1. 发明申请
    • LINEAR TRANSCONDUCTOR FOR RF COMMUNICATIONS
    • 用于射频通信的线性TRANSCONDUCTOR
    • US20120043996A1
    • 2012-02-23
    • US13288265
    • 2011-11-03
    • Harish MuthaliKenneth Charles Barnett
    • Harish MuthaliKenneth Charles Barnett
    • H02M11/00
    • H03F3/45188H03F1/32H03F1/3211H03F3/45H03F3/45659H03F2200/357H03F2203/45068H03F2203/45318H03F2203/45352
    • The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground.
    • 本专利申请包括具有至少一个输入和至少一个输出的线性跨导体,包括具有多个晶体管和多个输入的差分放大器,其中放大输入信号的差异,具有多个输入信号的共源共栅电路 晶体管,其中晶体管可操作地连接到差分放大器,其中线性跨导器的输入和输出之间的反向隔离通过将多个晶体管中的至少一个晶体管安装到线性跨导器的输入和输出而被改善 作为堆叠在差分放大器的至少一个晶体管上的公共栅极的共源共栅电路,具有可操作地连接在共源共栅电路和电源电压之间的多个晶体管的有源负载和可操作地连接到所述串联电路之间的连接的辅助装置 有源负载,共源共栅器件和地。
    • 2. 发明授权
    • Linear transconductor for RF communications
    • 用于射频通信的线性跨导器
    • US08086207B2
    • 2011-12-27
    • US11761947
    • 2007-06-12
    • Harish MuthaliKenneth Charles Barnett
    • Harish MuthaliKenneth Charles Barnett
    • H04B1/26H04B1/28
    • H03F3/45188H03F1/32H03F1/3211H03F3/45H03F3/45659H03F2200/357H03F2203/45068H03F2203/45318H03F2203/45352
    • The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground.
    • 本专利申请包括具有至少一个输入和至少一个输出的线性跨导体,包括具有多个晶体管和多个输入的差分放大器,其中放大输入信号的差异,具有多个输入信号的共源共栅电路 晶体管,其中晶体管可操作地连接到差分放大器,其中线性跨导器的输入和输出之间的反向隔离通过将多个晶体管中的至少一个晶体管安装到线性跨导器的输入和输出而被改善 作为堆叠在差分放大器的至少一个晶体管上的公共栅极的共源共栅电路,具有可操作地连接在共源共栅电路和电源电压之间的多个晶体管的有源负载和可操作地连接到所述串联电路之间的连接的辅助装置 有源负载,共源共栅器件和地。
    • 3. 发明授权
    • Latch structure, frequency divider, and methods for operating same
    • 锁存结构,分频器和操作方法
    • US08058901B2
    • 2011-11-15
    • US12552810
    • 2009-09-02
    • Kun ZhangKenneth Charles Barnett
    • Kun ZhangKenneth Charles Barnett
    • H03K19/173
    • H03K3/356121H03K5/1565H03K23/544
    • A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
    • 闩锁包括三个电路。 当D和CK均为高电平时,当第一输入(D)和第一时钟相位(CK)均为低电平时,第一电路将第一输出(QB)驱动到第一电平,并提供高阻抗( 当对D和CK应用不同的逻辑电平时,HI-Z)。 当DB和CKB均为高电平时,第三输入(DB)和互补时钟相位(CKB)均为低电平时,第二电路将第二输出(Q)驱动到第一电平,并提供HI-Z 当DB和CKB应用不同的逻辑电平时。 当第一和第二电路在Q和QB提供HI-Z时,第三电路维持Q和QB的电压。 使用这种锁存器构造的奇数分频器可以产生50%的占空比运算,而不会将输出脉冲宽度限制为输入周期的整数倍。
    • 5. 发明授权
    • Transmit power reduction for a wireless device with multiple transmit signal paths
    • 具有多个发射信号路径的无线设备的发射功率降低
    • US07660598B2
    • 2010-02-09
    • US11020054
    • 2004-12-21
    • Kenneth Charles BarnettCharles J. PersicoPaul Peterzell
    • Kenneth Charles BarnettCharles J. PersicoPaul Peterzell
    • H04B7/00
    • H04B7/0691H04B7/0404H04B7/0608H04B7/0619H04B7/10H04W52/221H04W52/42
    • A wireless device is equipped with multiple (e.g., two) antennas, which may be of different designs. Each antenna interacts with the wireless environment in a different manner and achieves different scattering effect. The wireless device has one transmit signal path for each antenna. Each transmit signal path generates an RF output signal for transmission from the associated antenna. The wireless device controls the operation of one or more transmit signal paths to achieve a larger received signal level at a receiving base station. The wireless device may (1) autonomously adjust the transmit signal path(s) without relying on any feedback from the base station or (2) adjust the transmit signal path(s) based on transmit power control (TPC) commands received from the base station. The wireless device may selectively enable and disable each transmit signal path, vary the phase and/or gain of each transmit signal path, and so on.
    • 无线设备配备有可以具有不同设计的多个(例如,两个)天线。 每个天线以不同的方式与无线环境进行互动,并实现不同的散射效果。 无线设备对于每个天线具有一个发射信号路径。 每个发射信号路径产生用于从相关天线发射的RF输出信号。 无线设备控制一个或多个发射信号路径的操作以在接收基站实现更大的接收信号电平。 无线设备可以(1)自主地调整发送信号路径,而不依赖于来自基站的任何反馈,或(2)基于从基站接收的发送功率控制(TPC)命令来调整发送信号路径 站。 无线设备可以选择性地启用和禁用每个发射信号路径,改变每个发射信号路径的相位和/或增益等等。
    • 7. 发明授权
    • Capacitance multiplier circuit
    • 电容倍增电路
    • US07598793B1
    • 2009-10-06
    • US12053388
    • 2008-03-21
    • Susanta SenguptaKenneth Charles Barnett
    • Susanta SenguptaKenneth Charles Barnett
    • H03H11/40
    • H03H11/405H03F3/45183H03F3/45659H03F2200/456H03F2203/45318H03F2203/45526H03F2203/45646H03H11/0416H03H11/483
    • A capacitance multiplier circuit is configured to sense a current through a capacitor in an RC filter of the circuit and to multiply the current so as to achieve a capacitance multiplier effect without adding additional circuitry or requiring additional power. The circuit includes an RC filter, a first signal path connected to a filter output, and a second signal path connected to an input to the filter. A current output through the filter (iout) is split between the two paths, sensed in the first path and multiplied in the second path. The multiplied current is fed back from the second path to the filter input to raise the effective capacitance of capacitor C. The capacitance multiplier circuit, in raising the effective capacitance of the capacitor in the filter, does not affect the frequency response, linearity performance and/or stability of the overall circuit.
    • 电容乘法器电路被配置为感测通过电路的RC滤波器中的电容器的电流,并且乘以电流以实现电容倍增器效应,而不增加附加电路或需要额外的功率。 电路包括RC滤波器,连接到滤波器输出的第一信号路径和连接到滤波器的输入端的第二信号路径。 通过滤波器(iout)的电流输出在两条路径之间分开,在第一路径中感测并在第二条路径中相乘。 倍增电流从第二路径反馈到滤波器输入,以提高电容器C的有效电容。电容乘法器电路在提高滤波器中的电容器的有效电容时不影响频率响应,线性性能和 /或整体电路的稳定性。
    • 9. 发明授权
    • Linear transconductor for RF communications
    • 用于射频通信的线性跨导器
    • US08385872B2
    • 2013-02-26
    • US13288265
    • 2011-11-03
    • Harish S. MuthaliKenneth Charles Barnett
    • Harish S. MuthaliKenneth Charles Barnett
    • H04B1/10H04B1/04
    • H03F3/45188H03F1/32H03F1/3211H03F3/45H03F3/45659H03F2200/357H03F2203/45068H03F2203/45318H03F2203/45352
    • The present patent application comprises a linear transconductor having at least one input and at least one output, comprising a differential amplifier having a plurality of transistors and a plurality of inputs, wherein a difference of input signals is amplified, a cascode circuit having a plurality of transistors, wherein the transistors are operably connected to the differential amplifier, wherein reverse isolation between an input and an output of the linear transconductor is improved by decoupling the input and the output of the linear transconductor by mounting at least one transistor of the plurality of transistors of the cascode circuit as a common-gate stacked on the at least one transistor of the differential amplifier, an active load having a plurality of transistors operably connected between the cascode circuit and supply voltage, and an auxiliary device operably connected to the connection between the active load, the cascode device and ground.
    • 本专利申请包括具有至少一个输入和至少一个输出的线性跨导体,包括具有多个晶体管和多个输入的差分放大器,其中放大输入信号的差异,具有多个输入信号的共源共栅电路 晶体管,其中晶体管可操作地连接到差分放大器,其中线性跨导器的输入和输出之间的反向隔离通过将多个晶体管中的至少一个晶体管安装到线性跨导器的输入和输出而被改善 作为堆叠在差分放大器的至少一个晶体管上的公共栅极的共源共栅电路,具有可操作地连接在共源共栅电路和电源电压之间的多个晶体管的有源负载和可操作地连接到所述串联电路之间的连接的辅助装置 有源负载,共源共栅器件和地。