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    • 5. 发明授权
    • High-speed low-power latches
    • 高速低功率锁存器
    • US08970272B2
    • 2015-03-03
    • US12121493
    • 2008-05-15
    • Kun ZhangHarish Muthali
    • Kun ZhangHarish Muthali
    • H03K3/356H03K3/017H03K3/3562H03K5/00H03K5/156
    • H03K3/356139H03K3/017H03K3/356121H03K3/35625H03K5/00006H03K5/1565
    • A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. A third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. In another aspect, a signal generator includes at least one latch and a control circuit. The latch(es) receive a clock signal and generate an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal and generates a control signal to adjust operation of the latch(es) to obtain 50% duty cycle for the feedback signal.
    • 高速低功耗锁存器包括三组晶体管。 第一组晶体管基于具有非轨至轨或轨至轨电压摆幅的时钟信号选择用于锁存器的跟踪模式或保持模式。 第二组晶体管基于输入信号捕获数据值,并在跟踪模式期间提供输出信号。 第三组晶体管存储数据值,并在保持模式期间提供输出信号。 输入和输出信号具有轨到轨电压摆幅。 在另一方面,信号发生器包括至少一个锁存器和控制电路。 锁存器接收时钟信号并产生输出信号。 控制电路感测从输出信号导出的反馈信号的占空比,并产生控制信号以调整锁存器的操作,以获得反馈信号的50%占空比。
    • 8. 发明申请
    • LATCH STRUCTURE, FREQUENCY DIVIDER, AND METHODS FOR OPERATING SAME
    • 绞合结构,频率分配器和操作方法
    • US20100073027A1
    • 2010-03-25
    • US12552810
    • 2009-09-02
    • Kun ZhangKenneth Barnett
    • Kun ZhangKenneth Barnett
    • H03K19/094
    • H03K3/356121H03K5/1565H03K23/544
    • A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
    • 闩锁包括三个电路。 当D和CK均为高电平时,当第一输入(D)和第一时钟相位(CK)均为低电平时,第一电路将第一输出(QB)驱动到第一电平,并提供高阻抗( 当对D和CK应用不同的逻辑电平时,HI-Z)。 当DB和CKB均为高电平时,第三输入(DB)和互补时钟相位(CKB)均为低电平时,第二电路将第二输出(Q)驱动到第一电平,并提供HI-Z 当DB和CKB应用不同的逻辑电平时。 当第一和第二电路在Q和QB提供HI-Z时,第三电路维持Q和QB的电压。 使用这种锁存器构造的奇数分频器可以产生50%的占空比运算,而不会将输出脉冲宽度限制为输入周期的整数倍。
    • 9. 发明申请
    • HIGH-SPEED LOW-POWER LATCHES
    • 高速低功率锁存器
    • US20090284288A1
    • 2009-11-19
    • US12121493
    • 2008-05-15
    • Kun ZhangHarish Muthali
    • Kun ZhangHarish Muthali
    • H03B19/06H03K3/356H03K3/017
    • H03K3/356139H03K3/017H03K3/356121H03K3/35625H03K5/00006H03K5/1565
    • A high-speed low-power latch includes three sets of transistors. A first set of transistors selects a tracking mode or a holding mode for the latch based on a clock signal having non-rail-to-rail or rail-to-rail voltage swing. A second set of transistors captures a data value based on an input signal and provides an output signal during the tracking mode. A third set of transistors stores the data value and provides the output signal during the holding mode. The input and output signals have rail-to-rail voltage swing. In another aspect, a signal generator includes at least one latch and a control circuit. The latch(es) receive a clock signal and generate an output signal. The control circuit senses a duty cycle of a feedback signal derived from the output signal and generates a control signal to adjust operation of the latch(es) to obtain 50% duty cycle for the feedback signal.
    • 高速低功耗锁存器包括三组晶体管。 第一组晶体管基于具有非轨至轨或轨至轨电压摆幅的时钟信号选择用于锁存器的跟踪模式或保持模式。 第二组晶体管基于输入信号捕获数据值,并在跟踪模式期间提供输出信号。 第三组晶体管存储数据值,并在保持模式期间提供输出信号。 输入和输出信号具有轨到轨电压摆幅。 在另一方面,信号发生器包括至少一个锁存器和控制电路。 锁存器接收时钟信号并产生输出信号。 控制电路感测从输出信号导出的反馈信号的占空比,并产生控制信号以调整锁存器的操作,以获得反馈信号的50%占空比。