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    • 1. 发明申请
    • LATCH STRUCTURE, FREQUENCY DIVIDER, AND METHODS FOR OPERATING SAME
    • 绞合结构,频率分配器和操作方法
    • US20100073027A1
    • 2010-03-25
    • US12552810
    • 2009-09-02
    • Kun ZhangKenneth Barnett
    • Kun ZhangKenneth Barnett
    • H03K19/094
    • H03K3/356121H03K5/1565H03K23/544
    • A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
    • 闩锁包括三个电路。 当D和CK均为高电平时,当第一输入(D)和第一时钟相位(CK)均为低电平时,第一电路将第一输出(QB)驱动到第一电平,并提供高阻抗( 当对D和CK应用不同的逻辑电平时,HI-Z)。 当DB和CKB均为高电平时,第三输入(DB)和互补时钟相位(CKB)均为低电平时,第二电路将第二输出(Q)驱动到第一电平,并提供HI-Z 当DB和CKB应用不同的逻辑电平时。 当第一和第二电路在Q和QB提供HI-Z时,第三电路维持Q和QB的电压。 使用这种锁存器构造的奇数分频器可以产生50%的占空比运算,而不会将输出脉冲宽度限制为输入周期的整数倍。
    • 2. 发明授权
    • Latch structure, frequency divider, and methods for operating same
    • 锁存结构,分频器和操作方法
    • US08519742B2
    • 2013-08-27
    • US13253350
    • 2011-10-05
    • Kun ZhangKenneth Barnett
    • Kun ZhangKenneth Barnett
    • H03K19/173
    • H03K3/356121H03K5/1565H03K23/544
    • A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.
    • 闩锁包括三个电路。 当D和CK均为高电平时,当第一输入(D)和第一时钟相位(CK)均为低电平时,第一电路将第一输出(QB)驱动到第一电平,并提供高阻抗( 当对D和CK应用不同的逻辑电平时,HI-Z)。 当DB和CKB均为高电平时,第三输入(DB)和互补时钟相位(CKB)均为低电平时,第二电路将第二输出(Q)驱动到第一电平,并提供HI-Z 当DB和CKB应用不同的逻辑电平时。 当第一和第二电路在Q和QB提供HI-Z时,第三电路维持Q和QB的电压。 使用这种锁存器构造的奇数分频器可以产生50%的占空比运算,而不会将输出脉冲宽度限制为输入周期的整数倍。