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    • 4. 发明授权
    • Memory system and method to reduce reflection and signal degradation
    • 记忆系统和方法减少反射和信号衰减
    • US07194572B2
    • 2007-03-20
    • US10638069
    • 2003-08-08
    • Michael W. LeddigeJames A. McCall
    • Michael W. LeddigeJames A. McCall
    • G06F12/00
    • G06F13/4239G11C5/04
    • Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.
    • 本发明的实施例提供了一种存储器命令和地址(CA)总线架构,其可以适应具有降低的信号劣化的较高CA数据输出频率。 对于本发明的一个实施例,CA在主板上被划分,并且CA信号分量被路由到两个DIMM /通道存储器总线设计的两个双列直插式存储器模块(DIMM)中的每一个。 然后,每个DIMM上的CA信号分量依次通过相应DIMM上的每个动态随机存取存储器(DRAM)芯片。 在一个实施例中,在路由每个DRAM之后,CA信号在DIMM上终止。 在替代实施例中,CA信号在每个相应的DIMM的最后一个DRAM处终止在管芯上。
    • 5. 发明授权
    • Method and apparatus for implementing a serial memory architecture
    • 实现串行存储器架构的方法和装置
    • US6144576A
    • 2000-11-07
    • US136797
    • 1998-08-19
    • Michael W. LeddigeBryce D. Horine
    • Michael W. LeddigeBryce D. Horine
    • G11C5/00G11C5/06
    • G11C5/063G11C5/04
    • A serial memory architecture. A memory subsystem includes a bus and a first memory module coupled to the bus. The first memory module has a first connector to receive bus signals from the bus and a second connector to output the bus signals. A second memory module has a first connector to receive the bus signals from the second connector of the first memory module. The bus signals are thereby routed through the memory modules in a serial manner. In one embodiment the memory modules include one or more 90.degree. routing paths between connectors and the devices of the memory modules. In one embodiment, trace lengths are matched.
    • 串行存储器架构。 存储器子系统包括总线和耦合到总线的第一存储器模块。 第一存储器模块具有用于从总线接收总线信号的第一连接器和用于输出总线信号的第二连接器。 第二存储器模块具有用于从第一存储器模块的第二连接器接收总线信号的第一连接器。 因此,总线信号以串行方式路由存储器模块。 在一个实施例中,存储器模块包括连接器和存储器模块的装置之间的一个或多个90°路由路径。 在一个实施例中,迹线长度匹配。
    • 10. 发明授权
    • Method for implementing multiple memory buses on a memory module
    • 在存储器模块上实现多个存储器总线的方法
    • US06477614B1
    • 2002-11-05
    • US09658293
    • 2000-09-08
    • Michael W. LeddigeBryce D. HorineRandy BonellaPeter D. MacWilliams
    • Michael W. LeddigeBryce D. HorineRandy BonellaPeter D. MacWilliams
    • G06F1206
    • G06F13/4256
    • A computer system memory module includes a bi-directional repeater hub that in a first direction takes as an input a memory bus signal in a first port, regenerates the memory signals, and outputs the regenerated memory signal at a second port as at least one separate signal for coupling to a memory bus for each of the regenerated separate signals. In a second direction, the bi-directional repeater hub takes as input at least one memory bus signal at the second port, regenerates each input memory bus signal, and outputs the regenerated memory signal at the first port for coupling to a memory bus. A method includes determining whether a memory device to which signals are addressed is on a first memory module. Signals are routed to a first memory bus on the first memory module connected to the memory device if the memory is on the first memory module. Signals are routed to a second memory bus on a second memory module if the memory device is not on the first memory module.
    • 计算机系统存储器模块包括双向中继器集线器,其在第一方向上将第一端口中的存储器总线信号作为输入,再生存储器信号,并将第二端口处的再生存储器信号作为至少一个单独的 信号,用于耦合到存储器总线,用于每个再生的分离信号。 在第二方向上,双向中继器集线器在第二端口处输入至少一个存储器总线信号,再生每个输入存储器总线信号,并在第一端口处输出再生的存储器信号以耦合到存储器总线。 一种方法包括确定信号被寻址的存储器件是否在第一存储器模块上。 如果存储器位于第一存储器模块上,则信号被路由到连接到存储器设备的第一存储器模块上的第一存储器总线。 如果存储设备不在第一个存储器模块上,则信号被路由到第二存储器模块上的第二存储器总线。