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1. 发明申请

US20140156933A1 System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions 有权
标题翻译：用于提高连续事务记忆区域吞吐量的系统，方法和装置
公开(公告)号：US20140156933A1
公开(公告)日：2014-06-05
申请号：US13691218
申请日：2012-11-30
申请人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
发明人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
IPC分类号： G06F12/08
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30043 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F11/1448 , G06F11/1469 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2201/84 , G06F2212/1016 , G06F2212/452 , G06F2212/507 , G06F2212/6042 , G06F2212/62 , G06F2212/621 , G06F2213/0026
摘要： Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.
摘要翻译：描述了使用TM区域指示符（或颜色）来提高TM吞吐量的系统，装置和方法。通过使用TM区域指标，年龄较小的TM区域可以在等待旧TM区域提交时，退出指令。

2. 发明申请

US20130262838A1 Memory Disambiguation Hardware To Support Software Binary Translation 有权
标题翻译：内存消歧硬件支持软件二进制翻译
公开(公告)号：US20130262838A1
公开(公告)日：2013-10-03
申请号：US13435165
申请日：2012-03-30
申请人： Muawya M. Al-Otoom , Paul Caprioli , Abhay S. Kanhere , Arvind Krishnaswamy , Omar M. Shaikh
发明人： Muawya M. Al-Otoom , Paul Caprioli , Abhay S. Kanhere , Arvind Krishnaswamy , Omar M. Shaikh
IPC分类号： G06F9/30
CPC分类号： G06F8/52 , G06F9/3834 , G06F9/3857
摘要： A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.
摘要翻译：提供了一种支持软件二进制翻译的内存消歧硬件的方法。该方法包括展开要在处理器内执行的一组指令，该组指令具有多个存储器操作。确定存储器操作的原始相对顺序。然后，在软件中检测和识别可能的重排序问题。重新排序问题是在第一存储器操作已经在存储器操作的原始顺序之前被重新排序并且相对于第二存储器操作而被重新排序的时候。解决了重新排序问题，并且传达到处理器的存储器操作的相对顺序。

3. 发明申请

US20140156978A1 Detecting and Filtering Biased Branches in Global Branch History 审中-公开
标题翻译：在全球分支机构历史中检测和筛选偏倚分支
公开(公告)号：US20140156978A1
公开(公告)日：2014-06-05
申请号：US13691049
申请日：2012-11-30
申请人： Muawya M. AL-OTOOM , Paul CAPRIOLI , Jeffrey J. COOK
发明人： Muawya M. AL-OTOOM , Paul CAPRIOLI , Jeffrey J. COOK
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： A processor includes an instruction pipeline for executing instructions including a branching instruction, a counter for counting times that the branching instruction is taken, a register for storing a global branch history as a function of a value of the counter, and a branch prediction unit for predicting branching based on the global branch history.
摘要翻译：处理器包括用于执行指令的指令流水线，所述指令包括分支指令，用于计数分支指令的计数次数的计数器，用于存储作为计数器的值的函数的全局分支历史的寄存器，以及分支预测单元，根据全球分支历史预测分支。

4. 发明申请

US20130311758A1 HARDWARE PROFILING MECHANISM TO ENABLE PAGE LEVEL AUTOMATIC BINARY TRANSLATION 有权
标题翻译：硬件配置机制启用页面级自动二进制翻译
公开(公告)号：US20130311758A1
公开(公告)日：2013-11-21
申请号：US13993792
申请日：2012-03-30
申请人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
发明人： Paul Caprioli , Matthew C. Merten , Muawya M. Al-Otoom , Omar M. Shaikh , Abhay S. Kanhere , Suresh Srinivas , Koichi Yamada , Vivek Thakkar , Pawel Osciak
IPC分类号： G06F9/38
CPC分类号： G06F11/3466 , G06F8/40 , G06F8/52 , G06F9/3017 , G06F9/3842 , G06F9/4552 , G06F11/073 , G06F11/3616 , G06F11/3652
摘要： A hardware profiling mechanism implemented by performance monitoring hardware enables page level automatic binary translation. The hardware during runtime identifies a code page in memory containing potentially optimizable instructions. The hardware requests allocation of a new page in memory associated with the code page, where the new page contains a collection of counters and each of the counters corresponds to one of the instructions in the code page. When the hardware detects a branch instruction having a branch target within the code page, it increments one of the counters that has the same position in the new page as the branch target in the code page. The execution of the code page is repeated and the counters are incremented when branch targets fall within the code page. The hardware then provides the counter values in the new page to a binary translator for binary translation.
摘要翻译：通过性能监控硬件实现的硬件剖析机制可实现页面级自动二进制翻译。运行期间的硬件标识内存中包含潜在优化指令的代码页。硬件请求与代码页相关联的内存中的新页面的分配，其中新页面包含计数器的集合，并且每个计数器对应于代码页中的指令之一。当硬件检测到在代码页内具有分支目标的分支指令时，它增加与代码页中的分支目标相同的新页面中具有相同位置的计数器之一。代码页的执行被重复，并且当分支目标落在代码页内时计数器递增。然后硬件将新页面中的计数器值提供给用于二进制转换的二进制转换器。

5. 发明申请

US20100306515A1 Predictors with Adaptive Prediction Threshold 失效
标题翻译：具有自适应预测阈值的预测器
公开(公告)号：US20100306515A1
公开(公告)日：2010-12-02
申请号：US12473764
申请日：2009-05-28
申请人： Muawya M. Al-Otoom , Timothy H. Heil , Anil Krishna , Ken V. Vu
发明人： Muawya M. Al-Otoom , Timothy H. Heil , Anil Krishna , Ken V. Vu
IPC分类号： G06F9/38
CPC分类号： G06F9/3848
摘要： An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that index into the PHT entries. A count value of a prediction state counter representing a prediction state of a prediction state machine for a PHT entry is obtained. Count values in a set of counters allocated to the entry in the PHT are changed based on the count value of the entry's prediction state counter. The prediction threshold of the prediction state machine for the entry may then be adjusted based on the changed count values in the set of counters, wherein the prediction threshold is adjusted by changing a count value in a prediction threshold counter in the entry, and wherein adjusting the prediction threshold redefines predictions provided by the prediction state machine.
摘要翻译：一种自适应预测阈值方案，用于通过观察索引到PHT条目中的分支或分支的全局倾向来动态地调整模式历史表（PHT）中条目的预测阈值。获得表示PHT条目的预测状态机的预测状态的预测状态计数器的计数值。分配给PHT中的条目的一组计数器中的计数值根据条目的预测状态计数器的计数值而改变。然后可以基于该组计数器中的改变的计数值来调整用于该条目的预测状态机的预测阈值，其中通过改变条目中的预测阈值计数器中的计数值来调整预测阈值，并且其中调整预测阈值重新定义了由预测状态机提供的预测。

6. 发明申请

US20170097826A1 System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions 审中-公开
公开(公告)号：US20170097826A1
公开(公告)日：2017-04-06
申请号：US15382476
申请日：2016-12-16
申请人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
发明人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
IPC分类号： G06F9/38 , G06F9/46 , G06F12/084 , G06F9/30 , G06F12/0875
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30043 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F11/1448 , G06F11/1469 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2201/84 , G06F2212/1016 , G06F2212/452 , G06F2212/507 , G06F2212/6042 , G06F2212/62 , G06F2212/621 , G06F2213/0026
摘要： Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

7. 发明授权

US08826257B2 Memory disambiguation hardware to support software binary translation 有权
标题翻译：内存消歧硬件支持软件二进制翻译
公开(公告)号：US08826257B2
公开(公告)日：2014-09-02
申请号：US13435165
申请日：2012-03-30
申请人： Muawya M. Al-Otoom , Paul Caprioli , Abhay S. Kanhere , Arvind Krishnaswamy , Omar M. Shaikh
发明人： Muawya M. Al-Otoom , Paul Caprioli , Abhay S. Kanhere , Arvind Krishnaswamy , Omar M. Shaikh
IPC分类号： G06F9/45
CPC分类号： G06F8/52 , G06F9/3834 , G06F9/3857
摘要： A method of memory disambiguation hardware to support software binary translation is provided. This method includes unrolling a set of instructions to be executed within a processor, the set of instructions having a number of memory operations. An original relative order of memory operations is determined. Then, possible reordering problems are detected and identified in software. The reordering problem being when a first memory operation has been reordered prior to and aliases to a second memory operation with respect to the original order of memory operations. The reordering problem is addressed and a relative order of memory operations to the processor is communicated.
摘要翻译：提供了一种支持软件二进制翻译的内存消歧硬件的方法。该方法包括展开要在处理器内执行的一组指令，该组指令具有多个存储器操作。确定存储器操作的原始相对顺序。然后，在软件中检测和识别可能的重排序问题。重新排序问题是在第一存储器操作已经在存储器操作的原始顺序之前被重新排序并且相对于第二存储器操作而被重新排序的时候。解决了重新排序问题，并且传达到处理器的存储器操作的相对顺序。

8. 发明申请

US20140089271A1 MEMORY ADDRESS ALIASING DETECTION 有权
标题翻译：存储器寻址检测
公开(公告)号：US20140089271A1
公开(公告)日：2014-03-27
申请号：US13628634
申请日：2012-09-27
申请人： Muawya M. AL-OTOOM , Paul CAPRIOLI , Ryan CARLSON , Ho-Seop KIM , Omar SHAIKH
发明人： Muawya M. AL-OTOOM , Paul CAPRIOLI , Ryan CARLSON , Ho-Seop KIM , Omar SHAIKH
IPC分类号： G06F7/00 , G06F17/30
CPC分类号： G06F9/3834 , G06F7/00 , G06F9/30043 , G06F9/3842 , G06F9/44 , G06F17/30
摘要： Method and apparatus to efficiently detect violations of data dependency relationships. A memory address associated with a computer instruction may be obtained. A current state of the memory address may be identified. The current state may include whether the memory address is associated with a read or a store instruction, and whether the memory address is associated with a set or a check. A previously accumulated state associated with the memory address may be retrieved from a data structure. The previously accumulated state may include whether the memory address was previously associated with a read or a store instruction, and whether the memory address was previously associated with a set or a check. If a transition from the previously accumulated state to the current state is invalid, a failure condition may be signaled.
摘要翻译：有效检测违反数据依赖关系的方法和装置。可以获得与计算机指令相关联的存储器地址。可以识别存储器地址的当前状态。当前状态可以包括存储器地址是否与读取或存储指令相关联，以及存储器地址是否与集合或检查相关联。可以从数据结构检索与存储器地址相关联的先前累积状态。先前累积的状态可以包括存储器地址是否先前与读取或存储指令相关联，以及存储器地址是否先前与集合或检查相关联。如果从先前累积状态到当前状态的转换无效，则可以发信号通知故障状态。

9. 发明授权

US09652234B2 Instruction and logic to control transfer in a partial binary translation system 有权
公开(公告)号：US09652234B2
公开(公告)日：2017-05-16
申请号：US13996352
申请日：2011-09-30
申请人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
发明人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.

10. 发明申请

US20170097891A1 System, Method, and Apparatus for Improving Throughput of Consecutive Transactional Memory Regions 审中-公开
公开(公告)号：US20170097891A1
公开(公告)日：2017-04-06
申请号：US15382462
申请日：2016-12-16
申请人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
发明人： Omar M. Shaikh , Ravi Rajwar , Paul Caprioli , Muawya M. Al-Otoom
IPC分类号： G06F12/0817 , G06F12/0842 , G06F9/38 , G06F11/14 , G06F9/46 , G06F9/30 , G06F12/084 , G06F12/0875
CPC分类号： G06F9/3855 , G06F9/3004 , G06F9/30043 , G06F9/3016 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3863 , G06F9/467 , G06F11/1448 , G06F11/1469 , G06F12/0828 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F2201/84 , G06F2212/1016 , G06F2212/452 , G06F2212/507 , G06F2212/6042 , G06F2212/62 , G06F2212/621 , G06F2213/0026
摘要： Systems, apparatuses, and methods for improving TM throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit.

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