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1. 发明授权

US09652234B2 Instruction and logic to control transfer in a partial binary translation system 有权
公开(公告)号：US09652234B2
公开(公告)日：2017-05-16
申请号：US13996352
申请日：2011-09-30
申请人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
发明人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.

2. 发明申请

US20130305019A1 Instruction and Logic to Control Transfer in a Partial Binary Translation System 有权
标题翻译：控制部分二进制翻译系统传输的指令和逻辑
公开(公告)号：US20130305019A1
公开(公告)日：2013-11-14
申请号：US13996352
申请日：2011-09-30
申请人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
发明人： Paul Caprioli , Martin G. Dixon , Brett L. Toll , Muawya M. Al-Otoom , Omar M. Shaikh
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/30174 , G06F9/30189 , G06F9/3808 , G06F9/3877 , G06F9/3887
摘要： A dynamic optimization of code for a processor-specific dynamic binary translation of hot code pages (e.g., frequently executed code pages) may be provided by a run-time translation layer. A method may be provided to use an instruction look-aside buffer (iTLB) to map original code pages and translated code pages. The method may comprise fetching an instruction from an original code page, determining whether the fetched instruction is a first instruction of a new code page and whether the original code page is deprecated. If both determinations return yes, the method may further comprise fetching a next instruction from a translated code page. If either determinations returns no, the method may further comprise decoding the instruction and fetching the next instruction from the original code page.
摘要翻译：可以由运行时转换层提供用于热代码页（例如，经常执行的代码页）的处理器特定的动态二进制转换的代码的动态优化。可以提供一种方法来使用指令后备缓冲器（iTLB）来映射原始代码页和转换的代码页。该方法可以包括从原始代码页获取指令，确定所提取的指令是否是新代码页的第一指令以及原始代码页是否已被弃用。如果两个确定返回是，该方法还可以包括从转换的代码页获取下一个指令。如果任一确定返回否，则该方法还可以包括解码指令并从原始代码页获取下一条指令。

3. 发明授权

US09569208B2 Compressed instruction format 有权
标题翻译：压缩指令格式
公开(公告)号：US09569208B2
公开(公告)日：2017-02-14
申请号：US14307468
申请日：2014-06-17
申请人： Robert Valentine , Doron Orenstein , Brett L. Toll
发明人： Robert Valentine , Doron Orenstein , Brett L. Toll
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F9/3816 , G06F9/382
摘要： A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.
摘要翻译：一种解码可变长度指令集中的指令的技术。在一个实施例中，描述了指令编码，其中支持遗留，现在和将来的指令集扩展，并且提供增加的功能，而不扩展代码大小，并且在一些情况下减少代码大小。

4. 发明申请

US20140189308A1 METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT DETECTION FUNCTIONALITY 有权
标题翻译：方法，装置，说明和逻辑提供矢量地址冲突检测功能
公开(公告)号：US20140189308A1
公开(公告)日：2014-07-03
申请号：US13731006
申请日：2012-12-29
申请人： Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Brett L. Toll , Mark J. Charney , Milind B. Girkar
发明人： Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Robert Valentine , Jesus Corbal , Brett L. Toll , Mark J. Charney , Milind B. Girkar
IPC分类号： G06F9/30
CPC分类号： G06F9/30021 , G06F9/30018 , G06F9/30036 , G06F9/30109 , G06F9/30145 , G06F9/30185 , G06F9/3838 , G06F9/3887
摘要： Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：指令和逻辑提供SIMD地址冲突检测功能。一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段存储用于存储器中的数据元素的偏移量。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储可变的第二多个位以存储具有每个偏移的掩码位的冲突掩码。响应于对向量冲突指令进行解码，执行单元将每个数据字段中的偏移量与每个较不重要的数据字段进行比较，以确定它们是否保持匹配的偏移，并且在目标寄存器中的相应冲突掩码中，设置对应于较少具有匹配偏移的重要数据字段。向量地址冲突检测可以与可变大小的元素一起使用，并生成冲突掩码来解决收集修改分散SIMD操作中的依赖关系。

5. 发明申请

US20140189307A1 METHODS, APPARATUS, INSTRUCTIONS, AND LOGIC TO PROVIDE VECTOR ADDRESS CONFLICT RESOLUTION WITH VECTOR POPULATION COUNT FUNCTIONALITY 有权
标题翻译：方法，设备，说明和逻辑提供向量地址冲突分解与向量人口计数功能
公开(公告)号：US20140189307A1
公开(公告)日：2014-07-03
申请号：US13731005
申请日：2012-12-29
申请人： Robert Valentine , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Brett L. Toll
发明人： Robert Valentine , Mark J. Charney , Jesus Corbal , Milind B. Girkar , Christopher J. Hughes , Elmoustapha Ould-Ahmed-Vall , Brett L. Toll
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F7/607 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3836 , G06F9/3887 , H03M7/20
摘要： Instructions and logic provide SIMD address conflict resolution with vector population count functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store a variable second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of bits set to one for corresponding data fields. Responsive to decoding a vector population count instruction, execution units count the number of bits set to one for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector population count instructions can be used with variable sized elements and conflict masks to generate iteration counts and completion masks to be used each iteration to resolve dependencies in gather-modify-scatter SIMD operations.
摘要翻译：指令和逻辑提供SIMD地址冲突解决与向量群体计数功能。一些实施例包括具有可变多个数据字段的寄存器的处理器，每个数据字段用于存储可变的第二多个位。目的地寄存器具有对应的数据字段，这些数据字段中的每一个用于存储为相应的数据字段设置为1的位数的计数。响应于对向量群体计数指令进行解码，执行单元对寄存器中的每个数据字段设置为1的位数进行计数，并将计数存储在第一目的地寄存器的相应数据字段中。矢量人口计数指令可用于可变大小的元素和冲突掩码，以生成迭代计数和完成掩码，以便在每次迭代中使用以解决聚集修改散射SIMD操作中的依赖关系。

6. 发明申请

US20140310505A1 COMPRESSED INSTRUCTION FORMAT 审中-公开
标题翻译：压缩指令格式
公开(公告)号：US20140310505A1
公开(公告)日：2014-10-16
申请号：US14307468
申请日：2014-06-17
申请人： Robert Valentine , Doron Orenstein , Brett L. Toll
发明人： Robert Valentine , Doron Orenstein , Brett L. Toll
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30145 , G06F9/30149 , G06F9/3017 , G06F9/30174 , G06F9/30178 , G06F9/30185 , G06F9/3816 , G06F9/382
摘要： A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present, and future instruction set extensions are supported, and increased functionality is provided, without expanding the code size and, in some cases, reducing the code size.
摘要翻译：一种解码可变长度指令集中的指令的技术。在一个实施例中，描述了指令编码，其中支持遗留，现在和将来的指令集扩展，并且提供增加的功能，而不扩展代码大小，并且在一些情况下减少代码大小。

7. 发明申请

US20140189321A1 INSTRUCTIONS AND LOGIC TO VECTORIZE CONDITIONAL LOOPS 有权
标题翻译：说明和逻辑来展示条件
公开(公告)号：US20140189321A1
公开(公告)日：2014-07-03
申请号：US13731809
申请日：2012-12-31
申请人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Brett L. Toll
发明人： Tal Uliel , Elmoustapha Ould-Ahmed-Vall , Brett L. Toll
IPC分类号： G06F9/38
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30025 , G06F9/30043 , G06F9/3013 , G06F9/30145 , G06F9/3016 , G06F15/8007
摘要： Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to specify a conditions mask register, and a destination parameter to specify a destination vector to hold n consecutive vector elements, each of the plurality of n consecutive vector elements having a same variable partition size of m bytes. In response to the processor instruction, data is copied from consecutive vector elements in the source vector, and expanded into unmasked vector elements of the specified destination vector, without copying data into masked vector elements of the destination vector, wherein n varies responsive to the processor instruction executed. The source vector may be a register and the destination vector may be in memory. Some embodiments store counts of the condition decisions. Alternative embodiments may store other data, for example such as target addresses, or table offsets, or indicators of processing directives, etc.
摘要翻译：指令和逻辑提供条件循环的向量化。矢量展开指令具有指定源矢量的参数，用于指定条件屏蔽寄存器的参数和用于指定保持n个连续矢量元素的目的地矢量的目的地参数，所述多个n个连续矢量元素中的每一个具有相同的矢量元素可变分区大小为m字节。响应于处理器指令，从源向量中的连续向量元素复制数据，并将其扩展到指定目标向量的未屏蔽向量元素，而不将数据复制到目标向量的被掩蔽向量元素中，其中n响应于处理器执行指令源向量可以是寄存器，并且目的地向量可以在存储器中。一些实施例存储条件决定的计数。替代实施例可以存储其他数据，例如目标地址或表偏移，或处理指令的指示符等。

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