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2. 发明申请

US20170177361A1 APPARATUS AND METHOD FOR ACCELERATING GRAPH ANALYTICS 审中-公开
公开(公告)号：US20170177361A1
公开(公告)日：2017-06-22
申请号：US14978229
申请日：2015-12-22
申请人： Michael Anderson , Sheng Li , Jong Soo Park , MD Mostafa Ali Patwary , Nadathur Rajagopalan Satish , Mikhail Smelyanskiy , Narayanan Sundaram
发明人： Michael Anderson , Sheng Li , Jong Soo Park , MD Mostafa Ali Patwary , Nadathur Rajagopalan Satish , Mikhail Smelyanskiy , Narayanan Sundaram
IPC分类号： G06F9/30 , G06F12/08 , G06F17/30 , G06F9/38
CPC分类号： G06F9/30036 , G06F9/30032 , G06F9/3877 , G06F12/0811 , G06F12/084 , G06F2212/455
摘要： An apparatus and method are described for accelerating graph analytics. For example, one embodiment of a processor comprises: an instruction fetch unit to fetch program code including set intersection and set union operations; a graph accelerator unit (GAU) to execute at least a first portion of the program code related to the set intersection and set union operations and generate results; and an execution unit to execute at least a second portion of the program code using the results provided from the GAU.

3. 发明申请

US20140089276A1 SEARCH UNIT TO ACCELERATE VARIABLE LENGTH COMPRESSION/DECOMPRESSION 有权
标题翻译：搜索单位以加速可变长度压缩/解压缩
公开(公告)号：US20140089276A1
公开(公告)日：2014-03-27
申请号：US13629467
申请日：2012-09-27
申请人： Nadathur Rajagopalan SATISH , Changkyu KIM , Jatin CHHUGANI
发明人： Nadathur Rajagopalan SATISH , Changkyu KIM , Jatin CHHUGANI
IPC分类号： G06F17/30
CPC分类号： H03M7/30
摘要： Systems and methods to accelerate compression and decompression with a search unit implemented in the processor core. According to an embodiment, a search unit may be implemented to perform compression or decompression on an input stream of data. The search unit may use a look-up table to identify appropriate compression or decompression symbols. The look-up table may be populated with a table derived using the variable length coding symbols of a sequence of vertices to be compressed or extracted from a received data stream to be decompressed. A comparator and a finite state machine may be implemented in the search unit to facilitate traversal of the look-up table.
摘要翻译：用处理器核心实现的搜索单元来加速压缩和解压缩的系统和方法。根据实施例，可以实现搜索单元以对输入的数据流执行压缩或解压缩。搜索单元可以使用查找表来标识适当的压缩或解压缩符号。查找表可以使用将要从要被解压缩的接收数据流压缩或提取的顶点序列的可变长度编码符号导出的表来填充。可以在搜索单元中实现比较器和有限状态机，以便于遍历查找表。

4. 发明授权

US08478941B2 Gather and scatter operations in multi-level memory hierarchy 有权
公开(公告)号：US08478941B2
公开(公告)日：2013-07-02
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

5. 发明申请

US20120290799A1 GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY 有权
标题翻译：多级记忆层级中的数学和散射运算
公开(公告)号：US20120290799A1
公开(公告)日：2012-11-15
申请号：US13557164
申请日：2012-07-24
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译：描述与多级缓存中的收集或散布操作有关的方法和装置。在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。还描述和要求保护其他实施例。

6. 发明授权

US08275805B2 Method of decreasing a total computation time for a visual simulation loop in a virtual world application 有权
标题翻译：降低虚拟世界应用程序中视觉仿真循环的总计算时间的方法
公开(公告)号：US08275805B2
公开(公告)日：2012-09-25
申请号：US12732392
申请日：2010-03-26
申请人： Jatin Chhugani , Bryan Catanzaro , Sanjeev Kumar , Changkyu Kim , Nadathur Rajagopalan Satish
发明人： Jatin Chhugani , Bryan Catanzaro , Sanjeev Kumar , Changkyu Kim , Nadathur Rajagopalan Satish
IPC分类号： G06F17/30
CPC分类号： G06T15/00 , G06T13/00 , G06T17/005 , G06T2200/28
摘要： A method of decreasing a total computation time for a visual simulation loop includes sharing a common data structure across each phase of the visual simulation loop by adapting the common data structure to a requirement for each particular phase prior to performing a computation for that particular phase.
摘要翻译：减少可视化仿真循环的总计算时间的方法包括通过在对该特定阶段执行计算之前通过将公共数据结构适应于每个特定阶段的需求来共享视觉仿真循环的每个阶段的公共数据结构。

7. 发明申请

US20110138122A1 GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY 有权
标题翻译：多级记忆层级中的数学和散射运算
公开(公告)号：US20110138122A1
公开(公告)日：2011-06-09
申请号：US12630826
申请日：2009-12-03
申请人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
发明人： Christopher J. Hughes , Yen-Kuang Chen , Changkyu Kim , Daehyun Kim , Victor W. Lee , Anthony-Trung D. Nguyen , Nadathur Rajagopalan Satish
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译：描述与多级缓存中的收集或散布操作有关的方法和装置。在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。还描述和要求保护其他实施例。

8. 发明申请

US20180308201A1 COMPUTE OPTIMIZATION MECHANISM 审中-公开
公开(公告)号：US20180308201A1
公开(公告)日：2018-10-25
申请号：US15494905
申请日：2017-04-24
申请人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
发明人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
IPC分类号： G06T1/20
CPC分类号： G06T1/20 , G06F9/3001 , G06F9/3017 , G06F9/3851 , G06F9/3887 , G06F9/3895 , G06F9/46 , G06N3/063 , G06T15/005 , G06T15/04 , G09G5/363
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes sorting logic to sort processing threads into thread groups based on bit depth of floating point thread operations.

9. 发明申请

US20140337580A1 GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY 审中-公开
标题翻译：多级记忆层级中的数学和散射运算
公开(公告)号：US20140337580A1
公开(公告)日：2014-11-13
申请号：US14337174
申请日：2014-07-21
申请人： CHRISTOPHER J. HUGHES , YEN-KUANG CHEN , CHANGKYU KIM , DAEHYUN KIM , VICTOR W. LEE , ANTHONY-TRUNG D. NGUYEN , NADATHUR RAJAGOPALAN SATISH
发明人： CHRISTOPHER J. HUGHES , YEN-KUANG CHEN , CHANGKYU KIM , DAEHYUN KIM , VICTOR W. LEE , ANTHONY-TRUNG D. NGUYEN , NADATHUR RAJAGOPALAN SATISH
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F9/30043 , G06F12/0802 , G06F12/0897 , G06F2212/62 , Y02D10/13
摘要： Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
摘要翻译：描述与多级缓存中的收集或散布操作有关的方法和装置。在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。还描述和要求保护其他实施例。

10. 发明授权

US08533432B2 Cache and/or socket sensitive multi-processor cores breadth-first traversal 有权
标题翻译：缓存和/或套接字敏感的多处理器核宽度优先遍历
公开(公告)号：US08533432B2
公开(公告)日：2013-09-10
申请号：US13629087
申请日：2012-09-27
申请人： Nadathur Rajagopalan Satish , Changkyu Kim , Jatin Chhugani , Jason D. Sewall
发明人： Nadathur Rajagopalan Satish , Changkyu Kim , Jatin Chhugani , Jason D. Sewall
IPC分类号： G06F9/38 , G06F9/06 , G06F15/80 , G06F13/14
CPC分类号： G06F9/52
摘要： Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are described. A vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. Potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. The threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed.
摘要翻译：描述了通过并行线程与缓存和/或套接字敏感的宽度优先遍历遍历图形的方法，装置和存储装置。可以使用顶点访问阵列（VIS）来跟踪所访问的图形顶点。 VIS可以分为VIS子阵列，考虑到LLC的缓存大小，以减少驱逐的可能性。可以使用潜在边界顶点阵列（PBV）来存储用于下一次迭代的潜在边界顶点，用于在当前迭代中被访问的顶点。为每个线程生成的PBV的数量可以考虑多个套接字，所采用的处理器核在其上分布。螺纹可以是负载平衡的; 可以考虑进一步的数据局部性意识以减少套接字间通信，和/或可以采用锁定和无原子的更新操作。

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