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1. 发明授权

US08847351B2 Integrated power amplifier with load inductor located under IC die 有权
标题翻译：集成功率放大器，负载电感位于IC芯片下方
公开(公告)号：US08847351B2
公开(公告)日：2014-09-30
申请号：US12705493
申请日：2010-02-12
申请人： Guy Klemens , Thomas A Myers , Norman L Frederick, Jr. , Yu Zhao , Babak Nejati , Nathan M Pletcher , Aristotele Hadjichristos
发明人： Guy Klemens , Thomas A Myers , Norman L Frederick, Jr. , Yu Zhao , Babak Nejati , Nathan M Pletcher , Aristotele Hadjichristos
IPC分类号： H01L27/08
CPC分类号： H03F3/195 , H01L23/645 , H01L23/66 , H01L2223/6655 , H01L2223/6661 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/19015 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.
摘要翻译：这里描述了紧凑的集成功率放大器。在示例性设计中，装置包括（i）具有用于功率放大器的至少一个晶体管的集成电路（IC）管芯，以及（ii）具有用于功率放大器的负载电感器的IC封装。 IC芯片安装在IC封装上，晶体管位于负载感应器上方。在示例性设计中，IC管芯包括放置在IC封装上的负载电感器上的晶体管歧管。晶体管制造在晶体管歧管中，在晶体管歧管的中心具有漏极连接，并且在晶体管歧管的两侧具有源极连接。 IC芯片和IC封装可以包括一个或多个附加的功率放大器。每个功率放大器的晶体管可以位于该功率放大器的负载电感上。

2. 发明授权

US08971830B2 Multi-mode multi-band power amplifier module 有权
标题翻译：多模式多频段功率放大器模块
公开(公告)号：US08971830B2
公开(公告)日：2015-03-03
申请号：US12575414
申请日：2009-10-07
申请人： Aristotle Hadjichristos , Puay Hoe See , Babak Nejati , Guy Klemens , Norman L Frederick, Jr. , Gurkanwal S Sahota , Marco Cassia , Nathan M Pletcher , Yu Zhao , Thomas A Myers
发明人： Aristotle Hadjichristos , Puay Hoe See , Babak Nejati , Guy Klemens , Norman L Frederick, Jr. , Gurkanwal S Sahota , Marco Cassia , Nathan M Pletcher , Yu Zhao , Thomas A Myers
IPC分类号： H01Q11/12 , H04B1/04 , H03F1/02 , H03F3/24 , H03F3/72
CPC分类号： H04B1/0458 , H03F1/0277 , H03F3/24 , H03F3/72 , H03F2203/7236 , H04B1/0483
摘要： A multi-mode multi-band power amplifier (PA) module is described. In an exemplary design, the PA module includes multiple power amplifiers, multiple matching circuits, and a set of switches. Each power amplifier provides power amplification for its input signal when selected. Each matching circuit provides impedance matching and filtering for its power amplifier and provides a respective output signal. The switches configure the power amplifiers to support multiple modes, with each mode being for a particular radio technology. Each power amplifier supports at least two modes. The PA module may further include a driver amplifier and an additional matching circuit. The driver amplifier amplifies an input signal and provides an amplified signal to the power amplifiers. The additional matching circuit combines the outputs of other matching circuits and provides an output signal with higher output power. The driver amplifier and the power amplifiers can support multiple output power levels.
摘要翻译：描述了多模式多频带功率放大器（PA）模块。在示例性设计中，PA模块包括多个功率放大器，多个匹配电路和一组开关。每个功率放大器在选择时为其输入信号提供功率放大。每个匹配电路为其功率放大器提供阻抗匹配和滤波，并提供相应的输出信号。这些开关配置功率放大器以支持多种模式，每种模式都适用于特定的无线电技术。每个功率放大器至少支持两种模式。 PA模块还可以包括驱动器放大器和附加匹配电路。驱动器放大器放大输入信号并向功率放大器提供放大的信号。附加匹配电路组合其他匹配电路的输出，并提供具有较高输出功率的输出信号。驱动器放大器和功率放大器可以支持多个输出功率电平。

3. 发明授权

US08773204B2 Amplifier with reduced source degeneration inductance 有权
标题翻译：具有降低的源极退化电感的放大器
公开(公告)号：US08773204B2
公开(公告)日：2014-07-08
申请号：US13372648
申请日：2012-02-14
申请人： Jose Cabanillas , Calogero D Presti , Norman L Frederick, Jr.
发明人： Jose Cabanillas , Calogero D Presti , Norman L Frederick, Jr.
IPC分类号： H03F1/14
CPC分类号： H03F1/347 , H03F1/223 , H03F1/565 , H03F3/193 , H03F3/245
摘要： Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.
摘要翻译：公开了用于减少不期望的源极退化电感的技术。在示例性设计中，装置包括第一和第二连接。第一连接包括作为放大器的源极退化电感的第一寄生电感。第二连接包括磁耦合到第一寄生电感的第二寄生电感，以减小放大器的源极退化电感。放大器（例如，单端功率放大器）可以经由第一连接耦合到电路接地。阻抗匹配电路可以耦合到放大器，并且可以包括经由第二连接耦合到电路接地的电路部件。为了获得第一和第二寄生电感之间的期望的磁耦合，第一连接可以被定位成足够靠近（例如，在第二连接的预定距离内）。

4. 发明授权

US08432237B2 Output circuit with integrated impedance matching, power combining and filtering for power amplifiers and other circuits 有权
标题翻译：具有集成阻抗匹配，功率放大器和其他电路的功率组合和滤波的输出电路
公开(公告)号：US08432237B2
公开(公告)日：2013-04-30
申请号：US12541831
申请日：2009-08-14
申请人： Guy Klemens , Nathan M Pletcher , Babak Nejati , Norman L Frederick , Thomas A Myers
发明人： Guy Klemens , Nathan M Pletcher , Babak Nejati , Norman L Frederick , Thomas A Myers
IPC分类号： H01P5/12 , H03H7/38
CPC分类号： H03H7/38 , H03F1/56 , H03F3/195 , H03F3/245 , H03F3/604 , H03F2200/108 , H03F2200/171 , H03F2200/222 , H03F2200/318 , H03F2200/387 , H03F2200/411 , H03F2200/414 , H03F2200/451 , H03H7/48 , H04B1/0483
摘要： An output circuit with integrated impedance matching, power combining, and filtering and suitable for use with power amplifiers and other circuits is described. In an exemplary design, an apparatus may include first and second circuits (e.g., power amplifiers) and an output circuit. The first circuit may provide a first single-ended signal and may have a first output impedance. The second circuit may provide a second single-ended signal and may have a second output impedance. The output circuit may include (i) first and second matching circuits that perform output impedance matching and filtering for the first and second circuits, (ii) a combiner (e.g., a summing node) that combines the first and second single-ended signals to obtain a combined single-ended signal, (iii) a third matching circuit that performs impedance matching and filtering for the combined single-ended signal, and (iv) switches to route the single-ended signals to different outputs.
摘要翻译：描述了具有集成阻抗匹配，功率组合和滤波并适用于功率放大器和其他电路的输出电路。在示例性设计中，装置可以包括第一和第二电路（例如，功率放大器）和输出电路。第一电路可以提供第一单端信号并且可以具有第一输出阻抗。第二电路可以提供第二单端信号并且可以具有第二输出阻抗。输出电路可以包括（i）对第一和第二电路执行输出阻抗匹配和滤波的第一和第二匹配电路，（ii）将第一和第二单端信号组合到的组合器（例如，求和节点）获得组合的单端信号，（iii）对组合的单端信号执行阻抗匹配和滤波的第三匹配电路，以及（iv）将单端信号路由到不同输出的开关。

5. 发明申请

US20110128084A1 METHODS AND APPARATUS FOR INDUCTORS WITH INTEGRATED PASSIVE AND ACTIVE ELEMENTS 有权
标题翻译：具有集成被动和主动元件的电感器的方法和装置
公开(公告)号：US20110128084A1
公开(公告)日：2011-06-02
申请号：US12628502
申请日：2009-12-01
申请人： Jean Jin , Aristotele Hadjichristos , Ockgoo Lee , Hongyan Yan , Guy Klemens , Maulin P. Bhagat , Thomas Myers , Norman L. Frederick , Junxiong Deng , Aleksandar Tasic , Bhushan S. Asuri , Mohammad Farazian
发明人： Jean Jin , Aristotele Hadjichristos , Ockgoo Lee , Hongyan Yan , Guy Klemens , Maulin P. Bhagat , Thomas Myers , Norman L. Frederick , Junxiong Deng , Aleksandar Tasic , Bhushan S. Asuri , Mohammad Farazian
IPC分类号： H03B5/08 , H01F17/00
CPC分类号： H01L25/16 , H01F17/0006 , H01F27/40 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits.
摘要翻译：描述了集成电路。集成电路包括在电感器中心具有大的空白区域的电感器。集成电路还包括附加电路。附加电路位于电感器中心的大空区域内。附加电路可以包括电容器组，晶体管，静电放电（ESD）保护电路和其它各种无源或有源电路。

6. 发明授权

US08633777B2 Methods and apparatus for inductors with integrated passive and active elements 有权
标题翻译：具有集成无源和有源元件的电感器的方法和装置
公开(公告)号：US08633777B2
公开(公告)日：2014-01-21
申请号：US12628502
申请日：2009-12-01
申请人： Zhang Jin , Aristotele Hadjichristos , Ockgoo Lee , Hongyan Yan , Guy Klemens , Maulin P. Bhagat , Thomas Myers , Norman L. Frederick , Junxiong Deng , Aleksandar Tasic , Bhushan S. Asuri , Mohammad Farazian
发明人： Zhang Jin , Aristotele Hadjichristos , Ockgoo Lee , Hongyan Yan , Guy Klemens , Maulin P. Bhagat , Thomas Myers , Norman L. Frederick , Junxiong Deng , Aleksandar Tasic , Bhushan S. Asuri , Mohammad Farazian
IPC分类号： H03B1/00
CPC分类号： H01L25/16 , H01F17/0006 , H01F27/40 , H01L23/645 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits.
摘要翻译：描述了集成电路。集成电路包括在电感器中心具有大的空白区域的电感器。集成电路还包括附加电路。附加电路位于电感器中心的大空区域内。附加电路可以包括电容器组，晶体管，静电放电（ESD）保护电路和其它各种无源或有源电路。

7. 发明申请

US20130207732A1 AMPLIFIER WITH REDUCED SOURCE DEGENERATION INDUCTANCE 有权
标题翻译：具有减少源衰减电感的放大器
公开(公告)号：US20130207732A1
公开(公告)日：2013-08-15
申请号：US13372648
申请日：2012-02-14
申请人： Jose Cabanillas , Calogero D. Presti , Norman L. Frederick, JR.
发明人： Jose Cabanillas , Calogero D. Presti , Norman L. Frederick, JR.
IPC分类号： H03F3/04 , H03F1/08
CPC分类号： H03F1/347 , H03F1/223 , H03F1/565 , H03F3/193 , H03F3/245
摘要： Techniques for reducing undesired source degeneration inductance are disclosed. In an exemplary design, an apparatus includes first and second connections. The first connection includes a first parasitic inductance acting as a source degeneration inductance of an amplifier. The second connection includes a second parasitic inductance magnetically coupled to the first parasitic inductance to reduce the source degeneration inductance of the amplifier. The amplifier (e.g., a single-ended power amplifier) may be coupled to circuit ground via the first connection. An impedance matching circuit may be coupled to the amplifier and may include a circuit component coupled to circuit ground via the second connection. The first connection may be located sufficiently close to (e.g., within a predetermined distance of) the second connection in order to obtain the desired magnetic coupling between the first and second parasitic inductances.
摘要翻译：公开了用于减少不期望的源极退化电感的技术。在示例性设计中，装置包括第一和第二连接。第一连接包括作为放大器的源极退化电感的第一寄生电感。第二连接包括磁耦合到第一寄生电感的第二寄生电感，以减小放大器的源极退化电感。放大器（例如，单端功率放大器）可以经由第一连接耦合到电路接地。阻抗匹配电路可以耦合到放大器，并且可以包括经由第二连接耦合到电路接地的电路部件。为了获得第一和第二寄生电感之间的期望的磁耦合，第一连接可以被定位成足够靠近（例如，在第二连接的预定距离内）。

8. 发明申请

US20100327976A1 INTEGRATED POWER AMPLIFIER WITH LOAD INDUCTOR LOCATED UNDER IC DIE 有权
标题翻译：集成功率放大器与负载电感位于IC DIE下
公开(公告)号：US20100327976A1
公开(公告)日：2010-12-30
申请号：US12705493
申请日：2010-02-12
申请人： Guy Klemens , Thomas A. Myers , Norman L. Frederick, JR. , Yu Zhao , Babak Nejati , Nathan M. Pletcher , Aristoteie Hadjichristos
发明人： Guy Klemens , Thomas A. Myers , Norman L. Frederick, JR. , Yu Zhao , Babak Nejati , Nathan M. Pletcher , Aristoteie Hadjichristos
IPC分类号： H03F3/16
CPC分类号： H03F3/195 , H01L23/645 , H01L23/66 , H01L2223/6655 , H01L2223/6661 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/1305 , H01L2924/19015 , H01L2924/3011 , H01L2924/00 , H01L2224/0401
摘要： A compact integrated power amplifier is described herein. In an exemplary design, an apparatus includes (i) an integrated circuit (IC) die having at least one transistor for a power amplifier and (ii) an IC package having a load inductor for the power amplifier. The IC die is mounted on the IC package with the transistor(s) located over the load inductor. In an exemplary design, the IC die includes a transistor manifold that is placed over the load inductor on the IC package. The transistor(s) are fabricated in the transistor manifold, have a drain connection in the center of the transistor manifold, and have source connections on two sides of the transistor manifold. The IC die and the IC package may include one or more additional power amplifiers. The transistor(s) for each power amplifier may be located over the load inductor for that power amplifier.
摘要翻译：这里描述了紧凑的集成功率放大器。在示例性设计中，装置包括（i）具有用于功率放大器的至少一个晶体管的集成电路（IC）管芯，以及（ii）具有用于功率放大器的负载电感器的IC封装。 IC芯片安装在IC封装上，晶体管位于负载感应器上方。在示例性设计中，IC管芯包括放置在IC封装上的负载电感器上的晶体管歧管。晶体管制造在晶体管歧管中，在晶体管歧管的中心具有漏极连接，并且在晶体管歧管的两侧具有源极连接。 IC芯片和IC封装可以包括一个或多个附加的功率放大器。每个功率放大器的晶体管可以位于该功率放大器的负载电感上。

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